Realization of vertical P/sup +/ walls through-wafer for bi-directional current and voltage power integrated devices

P/sup +/ walls through wafer can be considered as a region key in the 3D architecture of new bi-directional current and voltage power integrated devices. In this paper, we demonstrate the possibility of fabricating these P/sup +/ walls combining the deep RIE of silicon and deposit of boron doped polysilicon.