An 18.5ns 128MB SOI DRAM with a floating body cell

A dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate. A multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time. The 25.7ns virtually static RAM (VSRAM) mode is realized by taking advantage of the cell's quasi non-destructive read-out.

[1]  Tetsuya Iizuka,et al.  A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode , 1988 .

[2]  S. Okhonin,et al.  Principles of transient charge pumping on partially depleted SOI MOSFETs , 2002, IEEE Electron Device Letters.

[3]  R. Ranica,et al.  A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[4]  T. Ohsawa,et al.  Memory design using one-transistor gain cell on SOI , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[5]  Hiroaki Yamada,et al.  A memory using one-transistor gain cell on SOI(FBC) with performance suitable for embedded DRAM's , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[6]  Jean-Michel Sallese,et al.  A SOI capacitor-less 1T-DRAM concept , 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).