VC-1: a scalable graphics computer with virtual local frame buffers
暂无分享,去创建一个
[1] Gruia-Catalin Roman,et al. VLSI perspective of real-time hidden-surface elimination , 1981 .
[2] Henry Fuchs,et al. A sorting classification of parallel rendering , 1994, IEEE Computer Graphics and Applications.
[3] David Ellsworth,et al. Distributing display lists on a multicomputer , 1990, I3D '90.
[4] Bengt-Olaf Schneider. A Processor for an Object‐Oriented Rendering System , 1988, Comput. Graph. Forum.
[5] Steven E. Molnar,et al. Combining Z-buffer Engines for Higher-Speed Rendering , 1988, Advances in Computer Graphics Hardware.
[6] Richard Weinberg,et al. Parallel processing image synthesis and anti-aliasing , 1981, SIGGRAPH '81.
[7] Kurt Akeley,et al. Reality Engine graphics , 1993, SIGGRAPH.
[8] Neil Hunt,et al. The triangle processor and normal vector shader: a VLSI system for high performance graphics , 1988, SIGGRAPH.
[9] Jonathan Schaeffer,et al. A VLSI Architecture for Image Composition , 1988, Advances in Computer Graphics Hardware.
[10] Kurt Akeley,et al. The accumulation buffer: hardware support for high-quality rendering , 1990, SIGGRAPH.
[11] John G. Eyles,et al. PixelFlow: high-speed rendering using image composition , 1992, SIGGRAPH.
[12] 西村憲. A Parallel Architecture for Computer Graphics Based on the Conflict-Free Multiport Frame Buffer(無競合複数ポートフレームバッファに基づいたコンピュータグラフィックスのための並列アーキテクチャ) , 1995 .
[13] Michael Cox. Algorithms for parallel rendering , 1995 .