Impacts of Random Telegraph Noise (RTN) on Digital Circuits

Random telegraph noise (RTN) is one of the important dynamic variation sources in ultrascaled MOSFETs. In this paper, the recently focused ac trap effects of RTN in digital circuits and their impacts on circuit performance are systematically investigated. Instead of trap occupancy probability under dc bias condition (pdc), which is traditionally used for RTN characterization, ac trap occupancy probability (pac), i.e., the effective percentage of time trap being occupied under ac bias condition, is proposed and evaluated analytically to investigate the dynamic trapping/detrapping behavior of RTN. A simulation approach that fully integrates the dynamic properties of ac trap effects is presented for accurate simulation of RTN in digital circuits. The impacts of RTN on digital circuit performances, e.g., failure probabilities of SRAM cells and jitters of ring oscillators, are then evaluated by the simulations and verified against predictions based on pac. The results show that degradations are highly workload dependent and that pac is critical in accurately evaluating the RTN-induced performance degradation and variability. The results are helpful for robust and resilient circuit design.

[1]  Samuel Karlin,et al.  A First Course on Stochastic Processes , 1968 .

[2]  M. J. Kirton,et al.  Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/ƒ) noise , 1989 .

[3]  E. Klumperink,et al.  Modeling random telegraph noise under switched bias conditions using cyclostationary RTS noise , 2003 .

[4]  H. Wallinga,et al.  Modeling of RTS noise in MOSFETs under steady-state and large-signal excitation , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[5]  K. Takeuchi,et al.  Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude , 2006, 2009 Symposium on VLSI Technology.

[6]  Eric A. M. Klumperink,et al.  Low-Frequency Noise Phenomena in Switched MOSFETs , 2007, IEEE Journal of Solid-State Circuits.

[7]  K. Takeuchi,et al.  Statistical characterization of trap position, energy, amplitude and time constants by RTN measurement of multiple individual traps , 2010, 2010 International Electron Devices Meeting.

[8]  Yu Cao,et al.  Simulation of random telegraph Noise with 2-stage equivalent circuit , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  K. Takeuchi,et al.  Direct observation of RTN-induced SRAM failure by accelerated testing and its application to product reliability assessment , 2010, 2010 Symposium on VLSI Technology.

[10]  C. Fiegna,et al.  Reduction of RTS Noise in Small-Area MOSFETs Under Switched Bias Conditions and Forward Substrate Bias , 2010, IEEE Transactions on Electron Devices.

[11]  Kenneth L. Shepard,et al.  Random telegraph noise in 45-nm CMOS: Analysis using an on-chip test and measurement system , 2010, 2010 International Electron Devices Meeting.

[12]  Alper Demir,et al.  MUSTARD: A coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of Random Telegraph Noise on SRAMs and DRAMs , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[13]  Kazutoshi Kobayashi,et al.  Modeling of Random Telegraph Noise under circuit operation — Simulation and measurement of RTN-induced delay fluctuation , 2011, 2011 12th International Symposium on Quality Electronic Design.

[14]  E. Leobandung,et al.  Evaluation methodology for random telegraph noise effects in SRAM arrays , 2011, 2011 International Electron Devices Meeting.

[15]  B. Kaczer,et al.  Statistical Model for MOSFET Bias Temperature Instability Component Due to Charge Trapping , 2011, IEEE Transactions on Electron Devices.

[16]  D. Frank,et al.  Voltage and temperature dependence of random telegraph noise in highly scaled HKMG ETSOI nFETs and its impact on logic delay uncertainty , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[17]  M. Kobayashi,et al.  Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs , 2012, 2012 International Electron Devices Meeting.

[18]  Yu Wang,et al.  Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits , 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

[19]  T. Matsumoto,et al.  Impact of random telegraph noise on CMOS logic delay uncertainty under low voltage operation , 2012, 2012 International Electron Devices Meeting.

[20]  J. Suehle,et al.  Physical model for Random Telegraph Noise amplitudes and implications , 2012, 2012 IEEE Silicon Nanoelectronics Workshop (SNW).

[21]  N. Horiguchi,et al.  Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[22]  Gilson I. Wirth,et al.  Compact modeling and simulation of Random Telegraph Noise under non-stationary conditions in the presence of random dopants , 2012, Microelectron. Reliab..

[23]  Ru Huang,et al.  New insights into AC RTN in scaled high-к / metal-gate MOSFETs under digital circuit operations , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[24]  Tibor Grasser,et al.  Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities , 2012, Microelectron. Reliab..

[25]  C. Chuang,et al.  Impacts of Random Telegraph Noise on FinFET devices, 6T SRAM cell, and logic circuits , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[26]  Ru Huang,et al.  Deep understanding of AC RTN in MuGFETs through new characterization method and impacts on logic circuits , 2013, 2013 Symposium on VLSI Technology.

[27]  Tahui Wang,et al.  Statistical Characterization and Modeling of the Temporal Evolutions of $\Delta V_{\rm t}$ Distribution in NBTI Recovery in Nanometer MOSFETs , 2013, IEEE Transactions on Electron Devices.

[28]  Ru Huang,et al.  A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology , 2013, 2013 IEEE International Electron Devices Meeting.

[29]  C. Kim,et al.  RTN induced frequency shift measurements using a ring oscillator based circuit , 2013, 2013 Symposium on VLSI Technology.

[30]  J. Chen,et al.  Experimental study of channel doping concentration impacts on random telegraph signal noise and successful noise suppression by strain induced mobility enhancement , 2013, 2013 Symposium on VLSI Technology.

[31]  B. Kaczer,et al.  A unified perspective of RTN and BTI , 2014, 2014 IEEE International Reliability Physics Symposium.

[32]  Ru Huang,et al.  New insights into the design for end-of-life variability of NBTI in scaled high-κ/metal-gate Technology for the nano-reliability era , 2014, 2014 IEEE International Electron Devices Meeting.