Reactive Sampling for Efficient Defect Source Identification

Defectivity control in semiconductor manufacturing is crucial to improve the product quality and to reduce the production cost. When defects are detected, the objective is to identify the tool that generates them. Tool commonality analysis (TCA) is believed to be an efficient method for defect source identification. The critical element of successful TCA is that multiple entry lots within the same process flow are available for the analysis. Hence, since deployment of dynamic sampling strategies, lots selected for inspection are taken from different process flows at different manufacturing levels. In these cases, the TCA cannot identify the defect source but a set of potentially faulty tools. This paper consists in increasing the number of inspected lots that can be used for the TCA. The approach is a combination of two methods. The first one is the comparable lots identification processed by a sequence alignment algorithm. The second method is the reactive sampling algorithm based on the set covering model, this algorithm consists in sampling the minimal number of lots that cover the maximal number of potentially faulty tools. The industrial experiments of the proposed algorithms show a significant increase of number of available lots for analysis.

[1]  Claude Yugma,et al.  A smart sampling algorithm to minimize risk dynamically , 2010, 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

[2]  U. Kaempf,et al.  The binomial test: a simple tool to identify process problems , 1995 .

[3]  T. Grossman,et al.  Computational Experience with Approximation Algorithms for the Set Covering Problem , 1994 .

[4]  Jacques Pinaton,et al.  New methodology for modeling large scale manufacturing process: Using process mining methods and experts' knowledge , 2011, 2011 9th IEEE/ACS International Conference on Computer Systems and Applications (AICCSA).

[5]  Zhi-Gang Ren,et al.  New ideas for applying ant colony optimization to the set covering problem , 2010, Comput. Ind. Eng..

[6]  Stéphane Dauzère-Pérès,et al.  Optimized management of excursions in semiconductor manufacturing , 2011, Proceedings of the 2011 Winter Simulation Conference (WSC).

[7]  R. E. Langford,et al.  The identification and analysis of systematic yield loss , 2000, 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072).

[8]  L. K. Garling,et al.  Determining equipment performance using analysis of variance , 1990, IEEE/SEMI International Symposium on Semiconductor Manufacturing Science.

[9]  Ram Akella,et al.  Statistical methodology for yield enhancement via baseline reduction , 1998, IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168).

[10]  Francis J. Vasko,et al.  Using a facility location algorithm to solve large set covering problems , 1984 .

[11]  R.L. Guldi,et al.  In-line defect reduction from a historical perspective and its implications for future integrated circuit manufacturing , 2004, IEEE Transactions on Semiconductor Manufacturing.

[12]  Stéphane Dauzère-Pérès,et al.  Industrial implementation of a dynamic sampling algorithm in semiconductor manufacturing: Approach and challenges , 2012, Proceedings Title: Proceedings of the 2012 Winter Simulation Conference (WSC).

[13]  Guanghui Lan,et al.  An effective and simple heuristic for the set covering problem , 2007, Eur. J. Oper. Res..

[14]  D.K. de Vries,et al.  On the False-Positive Rate of Statistical Equipment Comparisons Based on the Kruskal–Wallis $H$ Statistic , 2007, IEEE Transactions on Semiconductor Manufacturing.

[15]  Wil M. P. van der Aalst,et al.  Trace Alignment in Process Mining: Opportunities for Process Diagnostics , 2010, BPM.

[16]  Toshihide Ibaraki,et al.  Logical analysis of numerical data , 1997, Math. Program..

[17]  Paolo Toth,et al.  An electromagnetism metaheuristic for the unicost set covering problem , 2010, Eur. J. Oper. Res..

[18]  J. McNames,et al.  Locating disturbances in semiconductor manufacturing with stepwise regression , 2005, IEEE Transactions on Semiconductor Manufacturing.

[19]  Francis J. Vasko,et al.  Optimal Selection of Ingot Sizes Via Set Covering , 1987, Oper. Res..

[20]  Wen-Chih Wang,et al.  Data mining for yield enhancement in semiconductor manufacturing and an empirical study , 2007, Expert Syst. Appl..

[21]  Rubén Ruiz,et al.  Operational planning and control of semiconductor wafer production , 2006 .

[22]  David W. Mount,et al.  Bioinformatics - sequence and genome analysis (2. ed.) , 2004 .

[23]  Matteo Fischetti,et al.  Solution of Large-Scale Railway Crew Planning Problems: the Italian Experience , 1999 .

[24]  Wil M. P. van der Aalst,et al.  Process diagnostics using trace alignment: Opportunities, issues, and challenges , 2012, Inf. Syst..

[25]  G. Y. Kong Tool commonality analysis for yield enhancement , 2002, 13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002 (Cat. No.02CH37259).

[26]  Efthymios Housos,et al.  Automatic Optimization of Subproblems in Scheduling Airline Crews , 1997 .

[27]  D. Malinaric,et al.  Case study for root cause analysis of yield problems , 2000, 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072).

[28]  Matteo Fischetti,et al.  Algorithms for the Set Covering Problem , 2000, Ann. Oper. Res..