论文信息 - Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications

Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (AVO) and cutoff frequency (fT ) of 25-nm gate-length FinFETs operated at low drain-current (I ds=10 muA/mum). SDE region optimization in 25-nm FinFETs results in exceptionally high values of AVO (~45 dB) and f T (~70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs

G. A. Armstrong | G.A. Armstrong | A. Kranti | A. Kranti

[1] V. Trivedi,et al. Source/drain-doping engineering for optimal nanoscale FinFET design , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

[2] C.R. Cleavelin,et al. Quantum-mechanical effects in trigate SOI MOSFETs , 2006, IEEE Transactions on Electron Devices.

[3] Abhinav Kranti,et al. Analysis of static and dynamic performance of short-channel double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors for improved cutoff frequency , 2005 .

[4] N. Collaert,et al. Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.

[5] Abhinav Kranti,et al. Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications , 2007 .

[6] G. A. Armstrong,et al. Device design considerations for nanoscale double and triple gate FinFETs , 2005, 2005 IEEE International SOI Conference Proceedings.

[7] Abhinav Kranti,et al. Performance assessment of nanoscale double- and triple-gate FinFETs , 2006 .

[8] Abhinav Kranti,et al. Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs : Analytical model and design considerations , 2006 .

[9] Abhinav Kranti,et al. Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications , 2004 .