Test item priority estimation for high parallel test efficiency under ATE debug time constraints

Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution.

[1]  Frank Neugebauer,et al.  Multi-site test of RF transceivers on low-cost digital ATE , 2011, 2011 IEEE International Test Conference.

[2]  Mark Elston,et al.  Parallel, multi-DUT testing in an open architecture test system , 2005, IEEE International Conference on Test, 2005..

[3]  Garry Moore,et al.  Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy , 2015, Proceedings of the 2015 International Conference on Microelectronic Test Structures.

[4]  Yasuhiro Takahashi,et al.  Multi Domain Test: Novel test strategy to reduce the Cost of Test , 2011, 29th VLSI Test Symposium.

[5]  Gerard Morin,et al.  Low cost wafer level parallel test strategy for reliability assessments in sub-32nm technology nodes , 2011, 2011 IEEE ICMTS International Conference on Microelectronic Test Structures.

[6]  Naveen Velamati,et al.  Analytical Model for Multi-site Efficiency with Parallel to Serial Test Times, Yield and Clustering , 2009, 2009 27th IEEE VLSI Test Symposium.

[7]  Krishnendu Chakrabarty,et al.  Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  R. H. Yeh.  A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability , 2015 .

[9]  J. Rivoir,et al.  Parallel test reduces cost of test more effectively than just a cheap tester , 2004, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585).

[10]  Vishwani D. Agrawal,et al.  Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing , 2015, 2015 IEEE 24th North Atlantic Test Workshop.

[11]  Jochen Rivoir.  Lowering cost of test: parallel test or low-cost ATE? , 2003, 2003 Test Symposium.

[12]  Krishnendu Chakrabarty,et al.  Recent advances in single- and multi-site test optimization for DVS-based SoCs , 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).