Online High-Power P-i-N Diode Chip Temperature Extraction and Prediction Method With Maximum Recovery Current di/dt

P-i-N diode chip temperature is a significant indicator when evaluating the reliability of high-power converters. The feasibility of state-of-the-art thermosensitive electrical parameter (TSEP) extraction strategies for a high-power module is investigated and the limitations of using forward voltage drop for high-power P-i-N diode TSEP are explored. In the widely employed half-bridge topology, by detailed analysis of the upper antiparallel diode reverse recovery process due to lower nonideal insulated-gate bipolar transistor switching behavior, the inherent monotonic relationship between the maximum recovery current rate did/dt and chip temperature is disclosed. The maximum did/dt during the recovery period is chosen as the better TSEP, which can accurately reflect P-i-N diode chip temperature variation. Fortunately, by monitoring the negative peak voltage on the parasitic inductor between the Kelvin and power emitters under different temperatures, the maximum recovery rate did/dt can be readily determined. Consequently, additional passive components are not required for P-i-N diode chip temperature extraction, which is practical and cost-effective for high-power applications. Finally, a dynamic switching characteristics test platform based on a half-bridge topology is designed and adopted to experimentally verify the theoretical analysis. The experimental results show that the dependence between P-i-N diode chip temperature and the maximum recovery did/dt is approximately linear. This leads to a 3-D lookup table that can be used to estimate online P-i-N diode chip temperature.

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