Design of Floating-Point Arithmetic Unit for Mobile 3D Graphics Applications

In this paper, two-stage pipelined floating-point arithmetic unit (FPAU) was designed. The FPAU processor supports fifteen operations and has area-efficient and low-latency architecture via dual-path computation scheme, new normalization circuit, and flagged prefix adder. The FPAU has about 4-ns delay time under 0.18㎛ CMOS standard cell library and consists of about 5,930 gates.