论文信息 - An NMOS 64b floating-point chip set

An NMOS 64b floating-point chip set

Three floating point arithmetic chips have been developed in a 1.5μm NMOS process. They are an adder, modified Wallace Tree multiplier, and a combinatorial divider. Speed of scalar operation is 490ns, 660ns and 1610ns, respectively.

W. McAllister | D. Zuras

[1] George S. Taylor. Radix 16 SRT dividers with overlapped quotient selection stages: A 225 nanosecond double precision divider for the S-1 Mark IIB , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).