Estimation of ground bounce effects on CMOS circuits

As chip density is increased, number of I/Os are increased, and clock driver and fan out drivers constitute a large part of the chip. However, simultaneous switching of these drivers produces undesired noise and voltage changes on the chip ground and V/sub dd/ rails. In this paper these noises are modeled and simple expressions are derived that can estimate the shape and the peak of these pulses. These models are derived for both the long channel and short channel CMOS devices. HSPICE simulations confirm the validity of these models.