Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster

Ultralow off-current (I<sub>off</sub> les 1 pA/mum) ldquosilicon on thin BOX (SOTB)rdquo CMOSFETs were fabricated in 65-nm technology. Gate-induced drain leakage (GIDL) was adequately reduced by controlling the gate-overlap length with an additional offset spacer. Small threshold-voltage (V<sub>th</sub>) variation under a wide-range back-gate-bias (V<sub>bg</sub>) condition and suppressed I<sub>off</sub> variation by V<sub>bg</sub> control were demonstrated. Faster inverter delay (tau<sub>pd</sub>) than conventional low-standby-power (LSTP) bulk CMOS was also achieved.

[1]  S. Maegawa,et al.  Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[2]  A. Asenov,et al.  Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET , 2008, IEEE Electron Device Letters.

[3]  T. Iwamatsu,et al.  Smallest Vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate , 2008, 2008 Symposium on VLSI Technology.

[4]  T. Ernst,et al.  Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications , 2007, 2007 IEEE International Electron Devices Meeting.

[5]  M. Yamaoka,et al.  Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[6]  Tsai-Sheng Gau,et al.  Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[7]  K. Ohuchi,et al.  Impact of BOX scaling on 30 nm gate length FD SOI MOSFET , 2005, 2005 IEEE International SOI Conference Proceedings.

[8]  S.Z. Chang,et al.  Ultra-low leakage 0.16 /spl mu/m CMOS for low-standby power applications , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[9]  Nobuyuki Sugii,et al.  Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integrated with Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode , 2008 .

[10]  X. Garros,et al.  FDSOI devices with thin BOX and ground plane integration for 32nm node and below , 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

[11]  Tze-Chiang Chen,et al.  Where CMOS is Going: Trendy Hype vs. Real Technology , 2006, IEEE Solid-State Circuits Newsletter.

[12]  K. Imai,et al.  Design Methodology of Body-Biasing Scheme for Low Power System LSI With Multi- $V_{\rm th}$ Transistors , 2007, IEEE Transactions on Electron Devices.

[13]  Nobuyuki Sugii,et al.  Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal–Oxide–Semiconductor and Its Impact on Decreasing Standby Leakage Current , 2009 .

[14]  J. Liaw,et al.  Leakage scaling in deep submicron CMOS for SoC , 2002 .

[15]  Takayasu Sakurai,et al.  Perspectives of Low-Power VLSI's , 2004 .

[16]  T. Hiramoto,et al.  Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX , 2007, IEEE Electron Device Letters.

[17]  T. Iwamatsu,et al.  Controllable Inverter Delay and Suppressing Vth Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture , 2007, 2007 IEEE International Electron Devices Meeting.

[18]  A. O. Adan,et al.  OFF-State leakage current mechanisms in bulkSi and SOI MOSFETs and their impact on CMOS ULSIs standby current , 2001 .