论文信息 - LNA design for on-chip RF test

LNA design for on-chip RF test

In this paper we present two CMOS LNA blocks designed for integration with other RF frontend blocks for on-chip test. Both of them are variants of the source degenerated LNA with embedded switches and/or a multiplexer, optimized with respect to their function and location. We discuss their functionality and performances in terms of test mode and the normal operation mode. The circuits are designed for 0.35mum CMOS process. Simulation results obtained at 2.4 GHz frequency, show a tradeoff between performance and testability. Nevertheless, the LNA circuit, which only uses embedded switches, proves a satisfactory design

Jerzy J. Dabrowski | Lei Zou | Rashad Ramzan

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