Architectural synthesis of large, nearly regular algorithms: design trajectory and environment

We address the question of mapping a large, nearly regular numerical algorithm on an architecture of parallel processors whose extent in space is fixed — a fixed size array. The method that we present is generic in the sense that the mapping procedure is independent of the size of the original problem but adapts itself to the limited processing memory resources of the target array. The size of the original problem enters only as a parameter. The method is implemented as a set of tools of our HiFi design system which may truly be called an “architecture compiler”. We give a description of the system and show examples as we go along.RésuméLes auteurs traitent le problème de la mise en őuvre ďun algorithme de grande taille et quasi régulier sur une architecture parallèle constituée ďun tableau de processeurs dont ľétendue spatiale est fixe. La méthode que nous présentons est générique dans le sens où la procédure de transformation de ľalgorithme vers ľarchitecture est indépendante de la taille du problème ďorigine (qui apparaît comme un simple paramètre) et s’adapte aux capacités limitées de traitement et de mémoire de la machine cible. La méthode est mise en ceuvre comme un ensemble ďoutils de notre environnement de conception HiFi qui peut être qualifié de compilateur ďarchitecture au plein sens du terme. Nous donnons une description du système appuyée par des exemples.

[1]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[2]  E.F. Deprettere,et al.  An application specific IC for digital signal processing: the floating point pipeline CORDIC processor , 1990, [Proceedings] EURO ASIC `90.

[3]  Gene H. Golub,et al.  Matrix computations , 1983 .

[4]  Lothar Thiele,et al.  Design of configurable processor arrays , 1990, IEEE International Symposium on Circuits and Systems.

[5]  Raymond E Miller.  Switching theory , 1979 .

[6]  K. Jainandunsing,et al.  A new class of parallel algorithms for solving systems of linear equations , 1989 .

[7]  James Lyle Peterson,et al.  Petri net theory and the modeling of systems , 1981 .

[8]  Pieter van der Wolf,et al.  On the architecture of a CAD framework: The NELSIS approach , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[9]  E.F. Deprettere,et al.  The synthesis and implementation of signal processing applications specific VLSI CORDIC arrays , 1990, IEEE International Symposium on Circuits and Systems.

[10]  Ed F. Deprettere,et al.  Systolic array implementation of nested loop programs , 1990, [1990] Proceedings of the International Conference on Application Specific Array Processors.

[11]  J.A.G. Jess,et al.  Synthesis of concurrent hardware structures , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[12]  Ed F. Deprettere,et al.  A design methodology for fixed-size systolic arrays , 1990, [1990] Proceedings of the International Conference on Application Specific Array Processors.

[13]  Lothar Thiele,et al.  On the design of piecewise regular processor arrays , 1989, IEEE International Symposium on Circuits and Systems,.

[14]  John W. Backus,et al.  Can programming be liberated from the von Neumann style?: a functional style and its algebra of programs , 1978, CACM.

[15]  Thomas Kailath,et al.  Regular iterative algorithms and their implementation on processor arrays , 1988, Proc. IEEE.

[16]  J. Bu,et al.  Systematic design of regular VLSI processor arrays , 1990 .