A low complexity LDPC-BCH concatenated decoder for NAND flash memory
暂无分享,去创建一个
Chuan Zhang | Jin Sha | Feng Yan | Zhongjie Chen | Feng Yan | Jin Sha | Chuan Zhang | Zhongjie Chen
[1] Thomas J. Richardson,et al. Error Floors of LDPC Codes , 2003 .
[2] Huang-Chang Lee,et al. Optimization Techniques for the Efficient Implementation of High-Rate Layered QC-LDPC Decoders , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] Khaled A. S. Abdel-Ghaffar,et al. Algebraic construction of quasi-cyclic LDPC codes for the AWGN and erasure channels , 2006, IEEE Transactions on Communications.
[4] R. Blahut. Theory and practice of error control codes , 1983 .
[5] P. Urard,et al. A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[6] Yeong-Luh Ueng,et al. A low-complexity LDPC decoder for NAND flash applications , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).
[7] Herbert O. Burton. Inversionless decoding of binary BCH codes , 1971, IEEE Trans. Inf. Theory.
[8] Nozomu Togawa,et al. Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm , 2005, 2005 International Conference on Computer Design.
[9] Jin Sha,et al. 4.7-Gb/s LDPC Decoder on GPU , 2018, IEEE Communications Letters.
[10] Trieu-Kien Truong,et al. VLSI design of inverse-free Berlekamp-Massey algorithm , 1991 .
[11] Daniel J. Costello,et al. LDPC block and convolutional codes based on circulant matrices , 2004, IEEE Transactions on Information Theory.
[12] Neal R. Mielke,et al. Reliability of Solid-State Drives Based on NAND Flash Memory , 2017, Proceedings of the IEEE.
[13] Qin Huang,et al. Quasi-Cyclic LDPC Codes: An Algebraic Construction, Rank Analysis, and Codes on Latin Squares , 2010, IEEE Transactions on Communications.
[14] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[15] Jian-Jia Weng,et al. BCH Code Selection and Iterative Decoding for BCH and LDPC Concatenated Coding System , 2013, IEEE Communications Letters.
[16] Huang-Chang Lee,et al. A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[17] Hsie-Chia Chang,et al. A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[18] Wei Shao,et al. Dispersed Array LDPC Codes and Decoder Architecture for NAND Flash Memory , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.