Piecewise analysis and modeling of circuit pack temperature cycling data

Temperature cycling environmental stress testing (EST) of circuit packs is a standard test procedure for the precipitation of latent defects in order to minimize early product lifecycle customer returns. EST is an expensive, energy-intensive bottleneck in the manufacturing process, one that is based on empiricisms that may be out of date. This presents great opportunity for optimization and test cost reduction. This paper describes the characterization of temperature cycling through analysis and modeling of process data in order to optimize the test parameters — ramp rate, temperature extremes, dwell times, and number of cycles. Failure data from circuit packs tested at a Lucent facility is analyzed using a regression technique and graphical inspection. The dwell and ramp periods of the test are considered in a piecewise manner. A cost model is applied based on distributions fitted to the failure data. The analysis yields a methodology for the dynamic, value-based optimization of temperature cycling EST.