A novel method for high-level synthesis of datapaths in digital filters using a moth-flame optimization algorithm

High-level synthesis (HLS) is one of the most important processes in digital VLSI circuit design. Owing to complexity and enormity of the design space in HLS problems, employing meta-heuristic methods and swarm intelligence has been considered as a highly favorable option when solving such problems. This research work proposes a moth-flame optimization (MFO) algorithm-based method for HLS of datapaths in digital filters, where scheduling, allocating, and binding steps were performed simultaneously. It was observed that the efficiency of the proposed method enjoyed an improved efficiency thanks to the mentioned simultaneous steps while being combined with the MFO algorithm. By comparing the performance of the proposed method with Genetic algorithm based method and particle swarm optimization based method for HLS of digital filters benchmarks, it can be inferred that the proposed method outperforms the other two methods in HLS of digital filters. This is evidently approved by a maximum improvement observed in the rates of the delay, the occupied area of the chip, and the power consumption for 2.99%, 6.58%, and 6.48%, respectively. In addition to the mentioned improvement, another striking characteristic of the proposed method is its fast runtime in reaching a response. This could significantly lower the costs while increasing the design speed of circuits having large dimensions. As well, an averagely 20% rise was also discerned in the algorithm runtime compared to the other two methods.

[1]  Daniele Loiacono,et al.  Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance , 2010 .

[2]  Seyed Mohammad Mirjalili,et al.  Moth-flame optimization algorithm: A novel nature-inspired heuristic paradigm , 2015, Knowl. Based Syst..

[3]  O. V. Nepomnyashchiy,et al.  The VLSI High-Level Synthesis for Building Onboard Spacecraft Control Systems , 2018 .

[4]  Raul Camposano,et al.  Path-based scheduling for synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Chee Peng Lim,et al.  An artificial bee colony algorithm with a Modified Choice Function for the traveling salesman problem , 2019, Swarm Evol. Comput..

[6]  Saraju P. Mohanty,et al.  Low-Power High-Level Synthesis for Nanoscale CMOS Circuits , 2008 .

[7]  Sabih H. Gerez,et al.  Algorithms for VLSI design automation , 1998 .

[8]  Seyyed Ali Hashemi,et al.  A novel particle swarm optimization for high-level synthesis of digital filters , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[9]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[10]  Jarmo Takala,et al.  A Programmable Max-Log-MAP Turbo Decoder Implementation , 2008, VLSI Design.

[11]  Alex K. Jones,et al.  Behavioral synthesis of data-dominated circuits for minimal energy implementation , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[12]  MirjaliliSeyedali Moth-flame optimization algorithm , 2015 .

[13]  Magdy A. Bayoumi,et al.  Multiple voltage-based scheduling methodology for low power in the high level synthesis , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[14]  Subhajit Das,et al.  VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach , 2018, Circuits Syst. Signal Process..

[15]  Denis Navarro,et al.  Optimized FPGA Implementation of Model Predictive Control for Embedded Systems Using High-Level Synthesis Tool , 2018, IEEE Transactions on Industrial Informatics.

[16]  Srinivas Katkoori,et al.  Tabu search based behavioural synthesis of low leakage datapaths , 2004, IEEE Computer Society Annual Symposium on VLSI.

[17]  Ramesh Karri,et al.  Securing Hardware Accelerators: A New Challenge for High-Level Synthesis , 2018, IEEE Embedded Systems Letters.

[18]  Gang Wang,et al.  Design space exploration using time and resource duality with the ant colony optimization , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[19]  Wayne H. Wolf,et al.  Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Rehab F. Abdel-Kader Particle Swarm Optimization for Constrained Instruction Scheduling , 2008, VLSI Design.

[21]  M. C. Bhuvaneswari,et al.  A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths , 2012, VLSI Design.

[22]  John A. Nestor,et al.  SALSA: a new approach to scheduling with timing constraints , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  N. Ranganathan,et al.  A game theoretic approach for power optimization during behavioral synthesis , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[24]  Anirban Sengupta,et al.  Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis , 2015, Appl. Math. Comput..

[25]  Dervis Karaboga,et al.  Solving Traveling Salesman Problem by Using Combinatorial Artificial Bee Colony Algorithms , 2019, Int. J. Artif. Intell. Tools.

[26]  Alice C. Parker,et al.  MAHA: A Program for Datapath Synthesis , 1986, DAC 1986.

[27]  Reza Sedaghat,et al.  Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration , 2011, 2011 12th International Symposium on Quality Electronic Design.

[28]  Yun Liang,et al.  COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[29]  Fabrizio Ferrandi,et al.  Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis , 2018, IEEE Design & Test.

[30]  Benjamin Carrión Schäfer,et al.  VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration , 2019, Integr..

[31]  Anirban Sengupta,et al.  TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[32]  Saraju P. Mohanty,et al.  Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[33]  Srinivas Devadas,et al.  Algorithms for hardware allocation in data path synthesis , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[34]  Garima,et al.  Design, implementation and performance comparison of multiplier topologies in power-delay space , 2016 .

[35]  M. C. Bhuvaneswari Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems , 2015 .

[36]  Jinjun Xiong,et al.  Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era , 2017, IEEE Micro.

[37]  Srinivas Katkoori,et al.  A genetic algorithm for the design space exploration of datapaths during high-level synthesis , 2006, IEEE Transactions on Evolutionary Computation.