A 4th-Order Continuous-Time Delta-Sigma Modulator Using 6-bit Double Noise-Shaped Quantizer
暂无分享,去创建一个
[1] Michael H. Perrott,et al. A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time � ADC With VCO-Based Integrator and Quantizer Implemented in 0 . 13 � m CMOS , 2009 .
[2] Un-Ku Moon,et al. A Third-Order DT $\Delta\Sigma$ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer , 2011, IEEE Journal of Solid-State Circuits.
[3] David A. Johns,et al. A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20MHz signal bandwidth , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
[4] D.A. Johns,et al. A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.
[5] Andrew Adams,et al. A 10/20/30/40 MHz feed-forward FIR DAC continuous-time ΔΣ ADC with robust blocker performance for radio receivers , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).
[6] C. Holuigue,et al. A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.
[7] Andrew Adams,et al. A 10/20/30/40 MHz Feedforward FIR DAC Continuous-Time $\Delta\Sigma$ ADC With Robust Blocker Performance for Radio Receivers , 2016, IEEE Journal of Solid-State Circuits.
[8] Bruce A. Wooley,et al. A 2.5-V sigma-delta modulator for broadband communications applications , 2001 .
[9] Enrique Prefasi,et al. Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer , 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).
[10] SeongHwan Cho,et al. A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.
[11] John G. Kauffman,et al. A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW , 2014, IEEE Journal of Solid-State Circuits.
[12] Thomas Blon,et al. A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB , 2006 .
[13] Un-Ku Moon,et al. A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer , 2013, IEEE Journal of Solid-State Circuits.
[14] Un-Ku Moon,et al. 74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain , 2009, IEEE Journal of Solid-State Circuits.
[15] M.Z. Straayer,et al. A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, IEEE Journal of Solid-State Circuits.
[16] Jose Silva-Martinez,et al. A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors , 2003, IEEE J. Solid State Circuits.
[17] Pavan Kumar Hanumolu,et al. A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications , 2015, IEEE Journal of Solid-State Circuits.
[18] Georges G. E. Gielen,et al. A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.
[19] Amr Elshazly,et al. A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and Measurement Techniques , 2014, IEEE Journal of Solid-State Circuits.
[20] Donald A. Kerth,et al. A 12-bit, 1-MHz, two-step flash ADC , 1989 .
[21] SeongHwan Cho,et al. A $148fs_{rms}$ Integrated Noise 4 MHz Bandwidth Second-Order $\Delta\Sigma$ Time-to-Digital Converter With Gated Switched-Ring Oscillator , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[22] Matthew Z. Straayer,et al. A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, IEEE Journal of Solid-State Circuits.
[23] M.Z. Straayer,et al. A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping , 2009, IEEE Journal of Solid-State Circuits.
[24] Taewook Kim,et al. A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator , 2016, IEEE J. Solid State Circuits.
[25] M.H. Perrott,et al. A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS , 2009, IEEE Journal of Solid-State Circuits.
[26] D.A. Johns,et al. A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth , 2006, IEEE Journal of Solid-State Circuits.
[27] Yuan Zhou,et al. A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector , 2015, IEEE Journal of Solid-State Circuits.
[28] Michael H. Perrott,et al. A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, VLSIC 2008.