A dual redundancy radiation-hardened Flip-Flop based on C-element in 65nm process

We propose a radiation-hardened flip-flop immune to the Single Event Upset (SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. We take advantage of the property of C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the Flip-Flop. The Flip-Flop was implemented using 48 transistors and occupied an area of 30.78 um2, using 65nm CMOS process. It consumed 22.6% less transistors as compared to the traditional SEU resilient TMR Flip-flop.

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