PolyDyn - Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs

Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this chapter, we present a SystemC™-based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. Our approach addresses reconfiguration already on application level enabling early exploration and analysis of the effects of DPR. Moreover it also allows quick implementation of such systems using our automatic synthesis flow.

[1]  Jürgen Becker,et al.  Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[2]  Frank Oppenheimer,et al.  SystemC Object-Oriented Extensions and Synthesis Features , 2002 .

[3]  Brad L. Hutchings,et al.  JHDL-an HDL for reconfigurable systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[4]  Wolfgang Nebel,et al.  OSSS+R: Modelling and Simulating Self-Reconfigurable Systems , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[5]  Martin Radetzki.  Synthesis of digital circuits from object oriented specifications , 2000 .

[6]  Kostas Masselos,et al.  System-level modeling of dynamically reconfigurable hardware with SystemC , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[7]  Ian Robertson,et al.  A design flow for partially reconfigurable hardware , 2004, TECS.

[8]  Patrick Lysaght,et al.  Self Controlling Dynamic Reconfiguration: A Case Study , 1999, FPL.

[9]  Hugo Hedberg,et al.  A complete MP3 decoder on a chip , 2005, 2005 IEEE International Conference on Microelectronic Systems Education (MSE'05).

[10]  Wolfgang Nebel,et al.  Designing for dynamic partially reconfigurable FPGAs with SystemC and OSSS , 2004, FDL.

[11]  Wayne Luk,et al.  High-level language extensions for run-time reconfigurable systems , 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

[12]  Kenichi Kuroda,et al.  Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems , 2008, J. Comput..

[13]  Giovanni De Micheli,et al.  Resolution of dynamic memory allocation and pointers for the behavioral synthesis form C , 2000, DATE '00.

[14]  Wolfgang Nebel,et al.  OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[15]  Fabrizio Ferrandi,et al.  SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture , 2006, ERSA.

[16]  Suleyman Malki,et al.  A hardware implementation of an MP3 decoder , 2003 .

[17]  Steve McKeever,et al.  Pebble: A Language for Parametrised and Reconfigurable Hardware Design , 1998, FPL.

[18]  Philipp A. Hartmann,et al.  ReChannel: Describing and simulating reconfigurable hardware in systemC , 2008, TODE.

[19]  Kostas Masselos,et al.  SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip , 2004, FDL.