Fast and accurate source-level simulation of software timing considering complex code optimizations

This paper presents an approach for accurately estimating the execution time of parallel software components in complex embedded systems. Timing annotations obtained from highly optimized binary code are added to the source code of software components which is then integrated into a SystemC transaction-level simulation. This approach allows a fast evaluation of software execution times while being as accurate as conventional instruction set simulators. By simulating binary-level control flow in parallel to the original functionality of the software, even compiler optimizations heavily modifying the structure of the generated code can be modeled accurately. Experimental results show that the presented method produces timing estimates within the same level of accuracy as an established commercial tool for cycle-accurate instruction set simulation while being at least 20 times faster.

[1]  Eric Cheung,et al.  Fast and accurate performance simulation of embedded software for MPSoC , 2009, 2009 Asia and South Pacific Design Automation Conference.

[2]  Ren-Song Tsay,et al.  Source-level timing annotation for fast and accurate TLM computation model generation , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[3]  Wolfgang Rosenstiel,et al.  Reconstructing Line References from Optimized Binary Code for Source-Level Annotation , 2010, FDL.

[4]  Christoph Cullmann,et al.  Data-Flow Based Detection of Loop Bounds , 2007, WCET.

[5]  Eugenio Villar,et al.  Fast instruction cache modeling for approximate timed HW/SW co-simulation , 2010, GLSVLSI '10.

[6]  Kun Lu,et al.  An approach to improve accuracy of source-level TLMs of embedded software , 2011, 2011 Design, Automation & Test in Europe.

[7]  Adam Donlin,et al.  Transaction level modeling: flows and use models , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

[8]  Alberto L. Sangiovanni-Vincentelli,et al.  Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor , 2008, 2008 Design, Automation and Test in Europe.

[9]  Zhonglei Wang,et al.  An efficient approach for system-level timing simulation of compiler-optimized embedded software , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[10]  Bernd Finkbeiner,et al.  Static Detection of Parametric Loop Bounds on C Code , 2009 .

[11]  Frédéric Pétrot,et al.  Automatic instrumentation of embedded software for high level hardware/software co-simulation , 2009, 2009 Asia and South Pacific Design Automation Conference.

[12]  Wolfgang Rosenstiel,et al.  High-performance timing simulation of embedded software , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[13]  Wolfgang Rosenstiel,et al.  Fast and accurate resource conflict simulation for performance analysis of multi-core systems , 2011, 2011 Design, Automation & Test in Europe.