An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection

A half-rate single-loop CDR with a new frequency detection scheme is introduced. The proposed frequency detector selects between the clock phases (I and Q) to reduce cycle slipping, hence improving lock time and capture range. This frequency detector, implemented within a 10Gb/s CDR in Fujitsu 65nm CMOS, consumes only 8mW, but improves the capture range by up to 3.6×. The measured capture range with the FD is from 8.675Gb/s to 11Gb/s.

[1]  B. Raeavi,et al.  A 2.5-Gb/sec 15-mW BiCMOS clock recovery circuit , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[2]  Keng-Jan Hsiao,et al.  A clock and data recovery circuit with wide linear range frequency detector , 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[3]  B. Razavi,et al.  A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector , 2001, IEEE J. Solid State Circuits.

[4]  Behzad Razavi,et al.  A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector , 2003, IEEE J. Solid State Circuits.

[5]  Donald Richman,et al.  Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television , 1954, Proceedings of the IRE.

[6]  Rong-Jyi Yang,et al.  A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet , 2004 .