Yield and reliability of MNOS EEPROM products
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Ken Uchida | Kazunori Furusawa | Takeshi Furuno | Masaaki Terasawa | Yoshiaki Kamigaki | S. Minami | Takaaki Hagiwara | K. Yamazaki | S. Minami | Y. Kamigaki | T. Hagiwara | K. Furusawa | T. Furuno | K. Uchida | M. Terasawa | K. Yamazaki
[1] Kazunori Furusawa,et al. Improvement of Written-State Retentivity by Scaling Down MNOS Memory Devices : Silicon Devices and Process Technologies( Solid State Devices and Materials 1) , 1988 .
[2] H. Katto,et al. Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM , 1985, IEEE Transactions on Electron Devices.
[3] S.W. Owen,et al. A 256K high performance CMOS EEPROM technology , 1985, 1985 International Electron Devices Meeting.
[4] H.A.R. Wegener,et al. Endurance model for textured-poly floating gate memories , 1984, 1984 International Electron Devices Meeting.
[5] Yoshiaki Kamigaki,et al. High‐resolution transmission electron microscopy study of 1.5 nm ultrathin tunnel oxides of metal‐nitride‐oxide‐silicon nonvolatile memory devices , 1988 .
[6] Takaaki Hagiwara,et al. Scaling Down MNOS Nonvolatile Memory Devices , 1982 .
[7] P.I. Suciu,et al. A temperature- and process-tolerant 64K EEPROM , 1985, IEEE Journal of Solid-State Circuits.
[8] Yoshiaki Kamigaki,et al. Thermal oxidation of silicon in various oxygen partial pressures diluted by nitrogen , 1977 .
[9] Y.W. Hu,et al. High-voltage regulation and process considerations for high-density 5 V-only E/sup 2/PROM's , 1983, IEEE Journal of Solid-State Circuits.
[10] Tim Haifley. Endurance of EEPROMs with On-Chip Error Correction , 1987, IEEE Transactions on Reliability.
[11] W. G. Ansley. Computation of integrated-circuit yields from the distribution of slice yields for the individual devices , 1968 .