Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits

In this paper, we present techniques to find an input vector that maximizes the intrinsic decoupling capacitance of a circuit. This input vector can be used to enhance the on-chip decoupling capacitance in the standby mode and when the macroblock is not used or disabled by certain applications. Enhancing the decoupling capacitance increases the effective charge stored on chip and also makes the power bus stiffer. This can reduce the voltage variations at nodes in the power distribution network. A genetic-algorithm-based technique and a guided randomized search with look-ahead-based technique are used to generate the input vector. Experimental results for the ISCAS85 benchmark circuits are also presented.

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