Delay and area optimization for discrete gate sizes under double-sided timing constraints

A three-step algorithm is presented for the discrete gate sizing problem of delay/area optimization under double-sided timing constraints. The problem is first formulated as a linear program. The solution to the linear problem is then mapped onto a permissible set. Using this set, the gate sizes are adjusted to satisfy the delay lower and upper bounds simultaneously. It is shown that the algorithm is able to find a near-optimal solution in a reasonable amount of time.