LASER: Latency-Aware Segment Relocation for non-volatile memory

In this work, we develop Latency-Aware Segment Relocation (LASER) which relocates a subset of segments of binary image to NVRAM to reduce program launch latency. A significant amount of time is spent on loading the binary image to main memory and initializing it. We develop a new system startup mechanism, to reduce the boot time by using selectively relocating read-only sections in NVRAM. We develop a model to determine the set of segments to be loaded into NVRAM given the maximum launch latency constraint and the physical latency of NVRAM. We implement LASER scheme to commercially available embedded systems (S5PC100 and Zynq7020). LASER-enabled systems achieve 54% and 38% reduction in boot time in S5PC100 and Zynq7020 systems, respectively.

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