tering into aregister whenever aredundant storage takes place. As aresult, theinternal powerandtheswitching activity oftheinput Increasing complexity ofcutting-edge applications forfutureandoutput ports oftheregister cells getseverely reduced. Thisseembedded systems demand evenhigher processor performance with lective blocking also reduces powerinthedownstream logic ofthe astrong consideration forbattery-life. Lowpoweroptimization blocked components, since theoutputs oftheblocked components techniques are, therefore, widely applied towards thedevelopmentremain unaffected foracertain number ofclock cycles. ofmodern Application Specific Instruction-Set Processors (ASIPs). Traditionally, RTL-based clock gating isperformed manually. Architecture Description Languages (ADLs) offer theASIPdesign-Withincreasing design complexity, automatic clockgating tools ersaquick andoptimal design convergence byautomatically gener- aregetting integrated into theexisting commercial synthesis flow. ating thesoftware tool-suite aswell astheRegister Transfer Level Thesetools perform clockgating atRTLabstraction. Thealgo(RTL) description oftheprocessor Theautomatically generatedrithms typically lookforenable flags inthelocality ofstorage eleprocessor description isthen subjected tothetraditional RTL-based ments orcompute theobservability ofdatapath blocks following the synthesis flow. Power-specific optimizations, often found inRTL- storage element. Forlarge datapath blocks, thecomputation ofthe based commercial tools, cannot takethefull advantage ofthear- observability isdemanding innature andtherefore, various approxchitectural knowledge embedded intheADLdescription, resultingimate heuristics areused. TheADL-driven processor development insub-optimal powerefficiency. Inthis paper, weaddress this is- flowcanleverage thearchitecture-specific knowledge toperform suebydescribing anefficient anduniversal technique ofautomatichighly effective clock gating, aswe willshowinthis paper. Our insertion ofgated clocks during theADL-based ASIPdesign flow. clock-gating mechanism isimplemented ontopoftheRTLprocesExperiments withASIPbenchmarks showthedramatic impact of sorsynthesis flowfromtheADL LISA[11]. Thebenefits ofthe ourapproach byreducing powerconsumption upto4100 percent ADL-based clock gating mechanism areevaluated using twomodcompared tonaive RTLsynthesis from ADL description, without ernpipelined embedded processors. Thecontribution ofthis paper anyincurred overheadfor areaandspeed. istopresent: