Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis

Common sub-expression elimination (CSE) serves as a useful optimization technique in the synthesis of arithmetic datapaths described at RTL. However, CSE has a limited potential for optimization when many common sub-expressions are not exposed. Given a suitable transformation of the polynomial system representation, which exposes many common sub-expressions, subsequent CSE can offer a higher degree of optimization. The objective of this paper is to develop algebraic techniques that perform such a transformation, and present a methodology to integrate it with CSE to further enhance the potential for optimization. In our experiments, we show that this integrated approach outperforms conventional methods in deriving area-efficient hardware implementations of polynomial systems.

[1]  Paolo Ienne,et al.  Improved use of the carry-save representation for the synthesis of complex arithmetic circuits , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[2]  Priyank Kalla,et al.  Optimization of polynomial datapaths using finite ring algebra , 2007, TODE.

[3]  Emmanuel Boutillon,et al.  Optimizing data flow graphs to minimize hardware implementation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[4]  Giovanni De Micheli,et al.  Application of symbolic computer algebra in high-level data-flow synthesis , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Ryan Kastner,et al.  Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[7]  Joel S. Cohen,et al.  Computer Algebra and Symbolic Computation: Mathematical Methods , 2003 .

[8]  Priyank Kalla,et al.  Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors , 2007, ICCAD 2007.

[9]  G. de Micheli,et al.  Polynomial methods for component matching and verification , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[10]  Xiaowei Shen,et al.  Using term rewriting systems to design and verify processors , 1999, IEEE Micro.

[11]  Zhibo Chen,et al.  On polynomial functions from Zn1 × Zn2 × ... × Znr to Zm , 1996, Discret. Math..

[12]  Bruno Buchberger,et al.  Some properties of Gröbner-bases for polynomial ideals , 1976, SIGS.

[13]  Giovanni De Micheli,et al.  Polynomial circuit models for component matching in high-level synthesis , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Bruno Buchberger,et al.  A theoretical basis for the reduction of polynomials to canonical forms , 1976, SIGS.

[15]  Alexandru Nicolau,et al.  Incremental tree height reduction for high level synthesis , 1991, 28th ACM/IEEE Design Automation Conference.

[16]  Giovanni De Micheli,et al.  Polynomial methods for allocating complex components , 1999, DATE '99.

[17]  V. J. Mathews,et al.  Polynomial Signal Processing , 2000 .

[18]  Priyank Kalla,et al.  Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs , 2006, IEEE Transactions on Computers.

[19]  Rajesh Gupta,et al.  Hardware/software co-design , 1996, Proc. IEEE.

[20]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .