论文信息 - 95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping

95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping

Low-power FPGA architecture is proposed based on fine-grained V DD control scheme called micro-VDD-hopping. Four configurable logic blocks (CLB) are grouped into one block where VDD is shared. In the micro-VDD-hopping scheme, V DD of each block is varied between the higher VDD (VDDH) and the lower VDD (VDDL) spatially and temporally to achieve lower power, while keeping performance undegraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. The proposed FPGA is fabricated using 035mum CMOS technology together with the conventional fixed-VDD FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the highest speed. Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGA is 2%

[1] Hiroshi Kawaguchi,et al. Observation of one-fifth-of-a-clock wake-up time of power-gated circuit , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[2] Li Shang,et al. Dynamic power consumption in Virtex™-II FPGA family , 2002, FPGA '02.

[3] H. Kawaguchi,et al. Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[4] Vaughn Betz,et al. Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[5] Anantha Chandrakasan,et al. Design methodology for fine-grained leakage control in MTCMOS , 2003, ISLPED '03.

[6] Shin'ichiro Mutoh,et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[7] T. Sakurai,et al. A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current , 2000, IEEE Journal of Solid-State Circuits.

[8] Hiroshi Kawaguchi,et al. A Controller LSI for Realizing VDD-Hopping Scheme with Off-the-Shelf Processors and Its Application to MPEG4 System , 2002 .