The exclusive domain of modeling and design for CPU packaging is beginning to find its way into the ASIC world as well. As the feature sizes decrease from 0.5 to 0.35 to 0.25 micron, the drivers become faster with sub-nsec transitions. Most of these ASICs service the ever widening word width, that has changed from 32 to 64 bits, and on to the wide word. Thus, in general, we have a gradual shift towards pad-limited designs that demand an ever-decreasing pitch, with very fast drivers switching simultaneously in large numbers. An increasing number of these ASICs dissipate more than the capability of ordinary plastic packages. This is a crowded, hot, and noisy environment that can be managed only by concurrent design of chip padout and package layout from an electrical perspective, and the system board/box design from a thermo-mechanical perspective. At the very least, it demands package selection based on electrical modeling of noise, generated by the chip and its package. This paper presents a study of three package styles for an ASIC with 270 signals. The design space for this chip type is expected to handle heat dissipation of 2 to 15 watts. That rules out most ordinary plastic packages, unless they are thermally enhanced. The packages selected for comparison, in this study, are of the enhanced BGA type. All of them use a heat spreader to which the chip is attached for thermal management. The study consists of: (a) an evaluation of how best to design the chip padout concurrently with the possibilities offered by the layout rules of these packages; (b) electrical models of these designs are used to calculate the various kinds of noise for each package type. The results are summarized for easy comparison, along with the assumptions made, to enable reasonable projections from these results.