Monitoração e roteamento adaptativo para fluxos QoS em NoCs

O crescente numero de aplicacoes executando em MPSoCs emergentes pode ser caracterizado pela sua alta demanda de computacao e comunicacao nas diferentes parte do chip. Os elementos de processamento que executam estas aplicacoes trazem uma natureza dinâmica e imprevisivel para o trafego em chip, devido a variabilidade nas taxas de injecao de dados que eles podem gerar. As redes em chip (NoC do ingles Network-on-Chip) sao as estruturas de comunicacao a serem utilizadas em tais sistemas, devido ao seu desempenho, confiabilidade e escalabilidade. Para lidar com o comportamento dinâmico do trafego de aplicacoes, varios metodos de adaptacao sao propostos em nivel de sistema (em tempo de execucao) e em nivel de arquitetura (em tempo de projeto). Esta Tese aborda o uso de tecnicas de adaptacao em NoCs em nivel de sistema e de arquitetura: dimensionamento de buffer e roteamento adaptativo. A primeira tecnica introduz um buffer de desacoplamento (D-buffer) no IP destino. Este buffer recebe dados da NoC com jitter, enquanto que o IP destino consome dados deste buffer na taxa da aplicacao, sem jitter. Dois problemas devem ser resolvidos para a implementacao de D-buffers: (i) qual tamanho este buffer deve possuir? (ii) quanto tempo deve ser esperado antes do inicio do consumo de dados (threshold)? Propoe-se aqui um metodo geral para definir o tamanho e threshold de D-buffers, considerando a influencia do empacotamento, arbitragem, roteamento e concorrencia entre fluxos. A segunda tecnica e um algoritmo de roteamento adaptativo para NoCs, onde o caminho entre o IPs origem e destino pode ser modificado devido a eventos de congestionamento. A maior parte das propostas do estado da arte possui uma visao limitada de congestionamento, considerando que cada roteador da NoC toma decisoes baseado no estado de seus vizinhos. Esta decisao local pode rotear pacotes a outras regioes congestionadas, o que pode tornar o algoritmo ineficiente. Este trabalho apresenta um novo metodo onde a analise de congestionamento considera informacoes de todos os roteadores no caminho entre a origem e destino. Este metodo e composto por um protocolo para estabelecimento de sessoes QoS, seguido de monitoracao distribuida e re-roteamento para regioes nao congestionadas. Resultados experimentais demonstram o impacto de fluxos multimidia com tamanhos de pacotes fixo e variavel (a partir de traces reais de trafego) no dimensionamento de buffers, e o percentual de violacoes de prazos em funcao do tamanho do D-buffer. Em termos de roteamento adaptativo, os resultados obtidos apresentam a influencia de diferentes niveis de localidade de trafego na latencia de pacotes, ocupacao da NoC e reatividade do roteamento adaptativo a eventos de congestionamento.

[1]  Li-Shiuan Peh,et al.  A Statistical Traffic Model for On-Chip Interconnection Networks , 2006, 14th IEEE International Symposium on Modeling, Analysis, and Simulation.

[2]  C. R. Jesshope,et al.  High performance communications in processor networks , 1989, ISCA '89.

[3]  Ewerson Carvalho.  Mapeamento dinâmico de tarefas em MPSoCs heterogêneos baseados em NoC , 2009 .

[4]  Shekhar Y. Borkar,et al.  iWarp: an integrated solution to high-speed parallel computing , 1988, Proceedings. SUPERCOMPUTING '88.

[5]  Théodore Marescaux,et al.  Distributed Congestion Control for Packet Switched Networks on Chip , 2005, PARCO.

[6]  L. Benini,et al.  Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.

[7]  Bo Friis Nielsen,et al.  A Markovian approach for modeling packet traffic with long-range dependence , 1998, IEEE J. Sel. Areas Commun..

[8]  Edson I. Moreno,et al.  Mapeamento e adaptação de rotas de comunicação em redes em chip , 2010 .

[9]  Fernando Gehm Moraes,et al.  A path-load based adaptive routing algorithm for networks-on-chip , 2009, SBCCI.

[10]  Partha Pratim Pande,et al.  Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.

[11]  Martin Reisslein,et al.  MPEG-4 and H.263 video traces for network performance evaluation , 2001, IEEE Netw..

[12]  Mohamed Ould-Khaoua,et al.  A performance model for wormhole-switched interconnection networks under self-similar traffic , 2004, IEEE Transactions on Computers.

[13]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[14]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[15]  Ranga Vemuri,et al.  optiMap: a tool for automated generation of NoC architectures using multi-port routers for FPGAs , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[16]  T.D. Hamalainen,et al.  Requirements for network-on-chip benchmarking , 2005, 2005 NORCHIP.

[17]  Kunle Olukotun,et al.  A chip prototyping substrate: the flexible architecture for simulation and testing (FAST) , 2005, CARN.

[18]  Aline Mello.  Qualidade de serviço em redes intra-chip: implementação e avaliação sobre a rede Hermes , 2006 .

[19]  Ljupco Kocarev,et al.  A ns-2 simulator utilizing chaotic maps for network-on-chip traffic analysis , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[20]  Luca Benini,et al.  Analyzing on-chip communication in a MPSoC environment , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[21]  Radu Marculescu,et al.  Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures , 2003, DATE.

[22]  Cristiane Raquel Woszezenki.  Alocação de tarefas e comunicação entre tarefas em MPSoCs , 2007 .

[23]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[24]  A. Afzali-Kusha,et al.  Minimizing Hot Spots in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections , 2006, 2006 International Symposium on System-on-Chip.

[25]  Ljupco Kocarev,et al.  On the impact of traffic statistics on quality of service for networks on chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[26]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[27]  Radu Marculescu,et al.  Towards Open Network-on-Chip Benchmarks , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[28]  Kees G. W. Goossens,et al.  Networks on silicon: combining best-effort and guaranteed services , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[29]  Hannu Tenhunen,et al.  Guest Editors' Introduction: Multiprocessor Systems-on-Chips , 2005, Computer.

[30]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[31]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[32]  Kees G. W. Goossens,et al.  Congestion-Controlled Best-Effort Communication for Networks-on-Chip , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[33]  Luca Benini,et al.  Powering networks on chips , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[34]  Kees G. W. Goossens,et al.  An event-based network-on-chip monitoring service , 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

[35]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[36]  Gul N. Khan,et al.  Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[37]  Grant Martin,et al.  System-on-Chip design , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

[38]  Fernando Gehm Moraes,et al.  A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures , 2009, CODES+ISSS '09.

[39]  Jorg Henkel,et al.  ROAdNoC: runtime observability for an adaptive network on chip architecture , 2008, ICCAD 2008.

[40]  Samuel dos Santos Marczak.  Implementação de uma infra-estrutura de monitoramento para avaliação de plataformas MPSOC baseada em NOC , 2010 .

[41]  Hoi-Jun Yoo,et al.  Cost-efficient Network-on-Chip Design Using Traffic Monitoring System , 2007 .

[42]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[43]  Chita R. Das,et al.  ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[44]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.

[45]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[46]  Antoine Fraboulet,et al.  Long-range dependence and on-chip processor traffic , 2009, Microprocess. Microsystems.

[47]  Yu Hen Hu,et al.  BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[48]  Ney Laert Vilar Calazans,et al.  Rate-based scheduling policy for QoS flows in networks on chip , 2007, 2007 IFIP International Conference on Very Large Scale Integration.

[49]  Flávio Rech Wagner,et al.  A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs , 2007, SBCCI.

[50]  Kees G. W. Goossens,et al.  NoC monitoring: impact on the design flow , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[51]  Srinivasan Murali,et al.  A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[52]  Fabien Clermidy,et al.  An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[53]  Fernando Gehm Moraes,et al.  Exploring NoC mapping strategies: an energy and timing aware technique , 2005, Design, Automation and Test in Europe.

[54]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[55]  Lionel M. Ni,et al.  The turn model for adaptive routing , 1998, ISCA '98.

[56]  M. Abid,et al.  Notice of Violation of IEEE Publication PrinciplesThe co-simulation interface SystemC/Matlab applied in JPEG algorithm , 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).

[57]  Radu Marculescu,et al.  On-chip traffic modeling and synthesis for MPEG-2 video applications , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[58]  Radu Marculescu,et al.  System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[59]  Lawrence T. Pileggi,et al.  An interconnect channel design methodology for high performance integrated circuits , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[60]  Radu Marculescu,et al.  Analysis and optimization of prediction-based flow control in networks-on-chip , 2008, TODE.

[61]  Murad S. Taqqu,et al.  On the Self-Similar Nature of Ethernet Traffic , 1993, SIGCOMM.

[62]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[63]  Daniel H. Linder,et al.  An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-Ary n-Cubes , 1994, IEEE Trans. Computers.

[64]  Ming Li,et al.  DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[65]  Masoud Daneshtalab,et al.  BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs , 2008, 2008 Design, Automation and Test in Europe.

[66]  M.W. El-Kharashi,et al.  A New Dynamic Routing Algorithm for Networks-on-Chips , 2007, 2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

[67]  Muhammad E. S. Elrabaa,et al.  A High-Throughput Network-on-Chip Architecture for Systems-on-Chip Interconnect , 2006, 2006 International Symposium on System-on-Chip.

[68]  Walter Willinger,et al.  Long-range dependence in variable-bit-rate video traffic , 1995, IEEE Trans. Commun..

[69]  L. Benini,et al.  Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[70]  Vincenzo Catania,et al.  Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip , 2008, IEEE Transactions on Computers.

[71]  Petru Eles,et al.  Buffer Space Optimisation with Communication Synthesis and Traffic Shaping for NoCs , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[72]  Fernando Gehm Moraes,et al.  Application driven traffic modeling for NoCs , 2006, SBCCI '06.

[73]  Giovanni De Micheli,et al.  A complete network-on-chip emulation framework , 2005, Design, Automation and Test in Europe.