论文信息 - VLSI design for an adaptive equalizer using a residue number system architecture for magnetic channels

VLSI design for an adaptive equalizer using a residue number system architecture for magnetic channels

This paper presents the design of an experimental ASIC for an all-digital adaptive equalizer for magnetic channels. The equalizer design, which is based on an RNS chip architecture, is presented at a system level, with particular attention to choices of word length, scaling, algorithm performance, and specifics of the RNS modules used to implement the LMS adaptive algorithm. It is believed that the short wordlength and high speed requirements of an adaptive equalizer in this particular application make it ideal for an efficient solution through RNS design techniques.

Inseop Lee | W. K. Jenkins

[1] Naresh R. Shanbhag,et al. A single-chip pipelined 2-D FIR filter using residue arithmetic , 1990, IEEE Conference on Aerospace and Electronics.

[2] C.M. Melas,et al. Adaptive equalization in magnetic-disk storage channels , 1990, IEEE Communications Magazine.

[3] Kyu Ho Park,et al. Efficient residue-to-binary conversion technique with rounding error compensation , 1991 .

[4] W. Kenneth Jenkins,et al. The use of residue number systems in the design of finite impulse response digital filters , 1977 .

[5] Jacques C. Rudell,et al. A 50 MHz eight-tap adaptive equalizer for partial-response channels , 1995 .

[6] Simon Haykin,et al. Adaptive filter theory (2nd ed.) , 1991 .