Improved FPGA implementation of Probabilistic Neural Network for neural decoding

Probabilistic Neural Network has been considered as providing superior performance for neural decoding. However, the huge computation burden costs high resource in FPGA, which limits its scalability. In this paper, an improved FPGA implementation of Probabilistic Neural Network for neural decoding is developed and evaluated on the Xilinx Virtex-5 platform. The proposed implementation reduces the resource utilization, and enhances the scalability of the FPGA implementation of the Probabilistic Neural Network greatly.

[1]  Fan Zhou,et al.  Field-programmable gate array implementation of a probabilistic neural network for motor cortical decoding in rats , 2010, Journal of Neuroscience Methods.

[2]  Jie Lin,et al.  Data Classification based on Artificial Neural Networks , 2008, 2008 International Conference on Apperceiving Computing and Intelligence Analysis.

[3]  Wang Yao,et al.  A Network Security Evaluation Model based on Common Criteria , 2008, 2008 International Conference on Apperceiving Computing and Intelligence Analysis.

[4]  Yi Yu,et al.  Neural decoding based on probabilistic neural network , 2010, Journal of Zhejiang University SCIENCE B.

[5]  Prabhas Chongstitvatana,et al.  FPGA-based online-learning using parallel genetic algorithm and neural network for ECG signal classification , 2010, ECTI-CON2010: The 2010 ECTI International Confernce on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology.

[6]  Jack E. Volder.  The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[7]  Yong Dou,et al.  Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor , 2008, 2008 10th IEEE International Conference on High Performance Computing and Communications.

[8]  Indranil Saha,et al.  journal homepage: www.elsevier.com/locate/neucom , 2022 .

[9]  Donald F. Specht,et al.  Probabilistic neural networks , 1990, Neural Networks.

[10]  Tülay Yildirim,et al.  FPGA implementation of a General Regression Neural Network: An embedded pattern classification system , 2010, Digit. Signal Process..

[11]  Marcian N. Cirstea,et al.  Direct Neural-Network Hardware-Implementation Algorithm , 2010, IEEE Transactions on Industrial Electronics.

[12]  S. Himavathi,et al.  Neural Network Implementation Using FPGA: Issues and Application , 2008 .