A Survey on Optical Network-on-Chip Architectures

Optical on-chip data transmission enabled by silicon photonics (SiP) is widely considered a key technology to overcome the bandwidth and energy limitations of electrical interconnects. The possibility of integrating optical links into the on-chip communication fabric has opened up a fascinating new research field—Optical Networks-on-Chip (ONoCs)—which has been gaining large interest by the community. SiP devices and materials, however, are still evolving, and dealing with optical data transmission on chip makes designers and researchers face a whole new set of obstacles and challenges. Designing efficient ONoCs is a challenging task and requires a detailed knowledge from on-chip traffic demands and patterns down to the physical layout and implications of integrating both electronic and photonic devices. In this paper, we provide an exhaustive review of recently proposed ONoC architectures, discuss their strengths and weaknesses, and outline active research areas. Moreover, we discuss recent research efforts in key enabling technologies, such as on-chip and adaptive laser sources, automatic synthesis tools, and ring heating techniques, which are essential to enable a widespread commercial adoption of ONoCs in the future.

[1]  Venkatesh Akella,et al.  Addressing system-level trimming issues in on-chip nanophotonic networks , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[2]  Smruti R. Sarangi,et al.  ColdBus: A Near-Optimal Power Efficient Optical Bus , 2015, 2015 IEEE 22nd International Conference on High Performance Computing (HiPC).

[3]  Rami G. Melhem,et al.  GASOLIN: Global Arbitration for Streams of Data in Optical Links , 2015, 2015 IEEE International Parallel and Distributed Processing Symposium.

[4]  M. Nikdast,et al.  An analytical study of process variations in silicon photonic integrated circuits , 2016, 2016 Photonics North (PN).

[5]  Alyssa B. Apsel,et al.  Leveraging Optical Technology in Future Bus-based Chip Multiprocessors , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[6]  Jung Ho Ahn,et al.  Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.

[7]  Wei Zhang,et al.  3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Aravind Srinivasan,et al.  A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[9]  Natalie D. Enright Jerger,et al.  QuT: A low-power optical Network-on-Chip , 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[10]  Ian O'Connor,et al.  Chameleon: Channel efficient Optical Network-on-Chip , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  Wei Zhang,et al.  A Hierarchical Hybrid Optical-Electronic Network-on-Chip , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[12]  Shekhar Y. Borkar Exascale Computing - A Fact or a Fiction? , 2013, IPDPS.

[13]  Chao Chen,et al.  Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture , 2013, IEEE Journal of Selected Topics in Quantum Electronics.

[14]  M. Romagnoli,et al.  An electrically pumped germanium laser. , 2012, Optics express.

[15]  C. Doerr,et al.  Low-Loss and Broadband Cantilever Couplers Between Standard Cleaved Fibers and High-Index-Contrast Si $_{3}$N $_{4}$ or Si Waveguides , 2010, IEEE Photonics Technology Letters.

[16]  Avinash Karanth Kodi,et al.  Cross-Chip: Low power processor-to-memory nanophotonic interconnect architecture , 2015, 2015 Sixth International Green and Sustainable Computing Conference (IGSC).

[17]  Ahmed Louri,et al.  3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[18]  Gabriela Nicolescu,et al.  Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[19]  Sudeep Pasricha,et al.  METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures , 2014, ACM Trans. Embed. Comput. Syst..

[20]  Mikko H. Lipasti,et al.  Wavelength stealing: An opportunistic approach to channel sharing in multi-chip photonic interconnects , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[21]  Nikolaos Hardavellas,et al.  Galaxy: a high-performance energy-efficient multi-chip architecture using photonic interconnects , 2014, ICS '14.

[22]  Yu Zhang,et al.  Firefly: illuminating future network-on-chip with nanophotonics , 2009, ISCA '09.

[23]  James Reinders,et al.  Intel Xeon Phi Coprocessor High Performance Programming , 2013 .

[24]  Michal Lipson,et al.  Athermal silicon microring resonators with titanium oxide cladding. , 2013, Optics express.

[25]  Mikko H. Lipasti,et al.  Light speed arbitration and flow control for nanophotonic interconnects , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[26]  Chen Sun,et al.  DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[27]  Kwang-Ting Cheng,et al.  Athermal silicon ring resonators clad with titanium dioxide for 1.3µm wavelength operation. , 2015, Optics express.

[28]  Cheng Li,et al.  LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Hugo Thienpont,et al.  Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects , 2009, 2009 17th IEEE Symposium on High Performance Interconnects.

[30]  M.K. Smit,et al.  8-channel AWG-based multiwavelength laser fabricated in a multi-project wafer run , 2011, IPRM 2011 - 23rd International Conference on Indium Phosphide and Related Materials.

[31]  Saurabh Dighe,et al.  An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[32]  Wei Zhang,et al.  Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[33]  José L. Abellán,et al.  Thermal management of manycore systems with silicon-photonic networks , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[34]  Bowen Zhang,et al.  A crosstalk-aware wavelength assignment method for optical network-on-chip , 2016, IEICE Electron. Express.

[35]  John Kim,et al.  FeatherWeight: Low-cost optical arbitration with QoS support , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[36]  Ian O'Connor,et al.  System level assessment of an optical NoC in an MPSoC platform , 2007 .

[37]  Christopher Batten,et al.  Silicon-photonic clos networks for global on-chip communication , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[38]  George Kurian,et al.  ATAC: A 1000-core cache-coherent processor with on-chip optical network , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

[39]  Jim Jeffers,et al.  Chapter 10 – Linux on the Coprocessor , 2013 .

[40]  Shaahin Hessabi,et al.  All-optical wavelength-routed NoC based on a novel hierarchical topology , 2011, Proceedings of the Fifth ACM/IEEE International Symposium.

[41]  Shaahin Hessabi,et al.  Scalable architecture for a contention-free optical network on-chip , 2012, J. Parallel Distributed Comput..

[42]  Sebastian Werner,et al.  Amon: An Advanced Mesh-like Optical NoC , 2015, 2015 IEEE 23rd Annual Symposium on High-Performance Interconnects.

[43]  Andrew B. Kahng,et al.  Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[44]  Li Zhou,et al.  PROBE: Prediction-based optical bandwidth scaling for energy-efficient NoCs , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[45]  Steven Swanson,et al.  Near-Data Processing: Insights from a MICRO-46 Workshop , 2014, IEEE Micro.

[46]  H. Jonathan Chao,et al.  BLOCON: A Bufferless Photonic Clos network-on-chip architecture , 2011, Proceedings of the Fifth ACM/IEEE International Symposium.

[47]  Avinash Karanth Kodi,et al.  CLAP-NET: Bandwidth adaptive optical crossbar architecture , 2017, J. Parallel Distributed Comput..

[48]  Xiaoge Zeng,et al.  Ultra-low-loss CMOS-compatible waveguide crossing arrays based on multimode Bloch waves and imaginary coupling. , 2013, Optics letters.

[49]  Ashok V. Krishnamoorthy,et al.  Silicon-photonic network architectures for scalable, power-efficient multi-chip systems , 2010, ISCA '10.

[50]  Jae Hoon Lee,et al.  Wavelength-based crosstalk-aware design for hybrid optical network-on-chip , 2017 .

[51]  Marco Gavanelli,et al.  Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[52]  Davide Bertozzi,et al.  Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive , 2016, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

[53]  Benjamin G Lee,et al.  Multichannel High-Bandwidth Coupling of Ultradense Silicon Photonic Waveguide Array to Standard-Pitch Fiber Array , 2011, Journal of Lightwave Technology.

[54]  Xiaowen Wu,et al.  SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor , 2014, JETC.

[55]  Sebastian Werner,et al.  Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[56]  Ajay Joshi,et al.  Sharing and placement of on-chip laser sources in silicon-photonic NoCs , 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[57]  R. Ho,et al.  2-pJ/bit (On-Chip) 10-Gb/s Digital CMOS Silicon Photonic Link , 2012, IEEE Photonics Technology Letters.

[58]  Mark Anders High-performance energy-efficient NoC fabrics: Evolution and future challenges , 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[59]  Nikil D. Dutt,et al.  ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip , 2008, 2008 Asia and South Pacific Design Automation Conference.

[60]  José L. Abellán,et al.  Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[61]  Hui Chen,et al.  On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions , 2005, IEEE Journal of Selected Topics in Quantum Electronics.

[62]  Bin Liu,et al.  A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array , 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

[63]  Jason Cong,et al.  Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects , 2013, TACO.

[64]  Ian O'Connor,et al.  Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology , 2011, 2011 Design, Automation & Test in Europe.

[65]  Luca P. Carloni,et al.  Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[66]  Kwang-Ting Cheng,et al.  DLPS: Dynamic laser power scaling for optical Network-on-Chip , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[67]  Ian O'Connor,et al.  Integrated Optical Interconnect Architectures for Embedded Systems , 2012 .

[68]  J. Michel,et al.  Ge-on-Si laser operating at room temperature. , 2010, Optics letters.

[69]  Huaxi Gu,et al.  Low-power low-latency optical network architecture for memory access communication , 2016, IEEE/OSA Journal of Optical Communications and Networking.

[70]  Ahmed Louri,et al.  Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[71]  Luca P. Carloni,et al.  Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors , 2008, IEEE Transactions on Computers.

[72]  Davide Bertozzi,et al.  Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization , 2015, 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing.

[73]  Timothy M. Jones,et al.  Coherence based message prediction for optically interconnected chip multiprocessors , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[74]  Cezar Reinbrecht,et al.  PHiCIT — Improving hierarchical Networks-on-Chip through 3D silicon photonics integration , 2015, 2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI).

[75]  David H. Albonesi,et al.  Phastlane: a rapid transit optical routing network , 2009, ISCA '09.

[76]  D. Livshits,et al.  Cost-effective WDM optical interconnects enabled by quantum dot comb lasers , 2010, OPTO.

[77]  Ian O'Connor,et al.  Towards Maximum Energy Efficiency in Nanophotonic Interconnects with Thermal-Aware On-Chip Laser Tuning , 2018, IEEE Transactions on Emerging Topics in Computing.

[78]  Javier Navaridas,et al.  Efficient sharing of optical resources in low-power optical networks-on-chip , 2017, IEEE/OSA Journal of Optical Communications and Networking.

[79]  Ulf Schlichtmann,et al.  PROTON: An automatic place-and-route tool for optical Networks-on-Chip , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[80]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[81]  Nikolaos Hardavellas,et al.  Parka: Thermally Insulated Nanophotonic Interconnects , 2015, NOCS.

[82]  Rami G. Melhem,et al.  Channel borrowing: an energy-efficient nanophotonic crossbar architecture with light-weight arbitration , 2012, ICS '12.

[83]  Lorenzo Pavesi,et al.  Silicon Photonics III , 2016 .

[84]  Davide Bertozzi,et al.  Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[85]  Mahdi Nikdast,et al.  Chip-Scale Silicon Photonic Interconnects: A Formal Study on Fabrication Non-Uniformity , 2016, Journal of Lightwave Technology.

[86]  Xiang Zhang,et al.  A multilayer nanophotonic interconnection network for on-chip many-core communications , 2010, Design Automation Conference.

[87]  Christopher Batten,et al.  Re-architecting DRAM memory systems with monolithically integrated silicon photonics , 2010, ISCA.

[88]  K. Bergman,et al.  Photonic interconnection network architectures using wavelength-selective spatial routing for chip-scale communications , 2012, IEEE/OSA Journal of Optical Communications and Networking.

[89]  Avinash Karanth Kodi,et al.  Exploring the Design of 64- and 256-Core Power Efficient Nanophotonic Interconnect , 2010, IEEE Journal of Selected Topics in Quantum Electronics.

[90]  Chen Sun,et al.  Addressing link-level design tradeoffs for integrated photonic interconnects , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[91]  Wei Zhang,et al.  A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[92]  Xi Chen,et al.  Reliability-Aware Design Flow for Silicon Photonics On-Chip Interconnect , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[93]  Nikos Hardavellas,et al.  Towards energy-efficient photonic interconnects , 2015, Photonics West - Optoelectronic Materials and Devices.

[94]  Luca P. Carloni,et al.  Photonic Network-on-Chip Design , 2013, Integrated Circuits and Systems.

[95]  Gilbert Hendry,et al.  Architectural Exploration of Chip-Scale Photonic Interconnection Network Designs Using Physical-Layer Analysis , 2010, Journal of Lightwave Technology.

[96]  G. Lynch,et al.  Variations in Synaptic Plasticity and Types of Memory in Corticohippocampal Networks , 1992, Journal of Cognitive Neuroscience.

[97]  Zhe Wang,et al.  Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[98]  Venkatesh Akella,et al.  Resilient microring resonator based photonic networks , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[99]  Jiang Xu,et al.  Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[100]  Smruti R. Sarangi,et al.  Active microring based tunable optical power splitters , 2016 .

[101]  F Y Gardes,et al.  40 Gb/s silicon photonics modulator for TE and TM polarisations. , 2011, Optics express.

[102]  Nikolaos Hardavellas,et al.  SLaC: Stage laser control for a flattened butterfly network , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[103]  Sudeep Pasricha,et al.  Run-time laser power management in photonic NoCs with on-chip semiconductor optical amplifiers , 2016, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

[104]  Xin Fu,et al.  Aurora: A Cross-Layer Solution for Thermally Resilient Photonic Network-on-Chip , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[105]  Chen Sun,et al.  Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System Using Real Application Workloads , 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium.

[106]  Xi Chen,et al.  Reliability Modeling and Management of Nanophotonic On-Chip Networks , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[107]  Luiz André Barroso,et al.  The Case for Energy-Proportional Computing , 2007, Computer.

[108]  Davide Bertozzi,et al.  A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[109]  Ulf Schlichtmann,et al.  PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer , 2016, ACM J. Emerg. Technol. Comput. Syst..

[110]  Y. Vlasov,et al.  Ultrafast-pulse self-phase modulation and third-order dispersion in Si photonic wire-waveguides. , 2006, Optics express.

[111]  John Kim,et al.  FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[112]  Nikolaos Hardavellas,et al.  EcoLaser: An adaptive laser control for energy-efficient on-chip photonic interconnects , 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[113]  Hui Chen,et al.  Predictions of CMOS compatible on-chip optical interconnect , 2005, SLIP '05.

[114]  Hui Li,et al.  Energy-efficient and temperature-stable high-speed VCSELs for optical interconnects , 2013, 2013 15th International Conference on Transparent Optical Networks (ICTON).

[115]  Fabrice Blache,et al.  High performance InP-based quantum dash semiconductor mode-locked lasers for optical communications , 2009, Bell Labs Technical Journal.

[116]  Xuezhe Zheng,et al.  Demonstration of 12.2% wall plug efficiency in uncooled single mode external-cavity tunable Si/III-V hybrid laser. , 2015, Optics express.

[117]  Xi Chen,et al.  Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication , 2011, JETC.