A 350-MS/s 3.3-V 8-bit CMOS D/A converter using a delayed driving scheme

This proceeding describes a 350-MS/s 8-bit CMOS D/A converter with 3.3-V power supply. A current source with a delayed driving scheme is developed. This driving scheme reduces fluctuation of internal node voltage of the current source and high-speed switching is realized. Two stages of latches are inserted into the matrix decoder for reducing glitch energy and for enhancing decoding speed. The D/A converter is fabricated in a 0.5-/spl mu/m CMOS process. Its settling time is less than 2.4 ns and it successfully operates at 350 MS/s.

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