A VLSI systolic array processor chip for computing joins in a relational database

Abstract In this paper, we describe the design and implementation of a VLSI chip for computing joins in a relational database that uses attribute-based storage schema. The chip design is based on a systolic architecture that fully utilizes the principles of pipelining and parallelism in order to obtain high speed and throughput. The architecture implements an improved version of the algorithm previously proposed by Kung and Lehman 1 . A partitioning technique proposed in Leiserson and Saxe 2 is incorporated in the algorithm in order to derive maximum utilization of the processors. Although the time complexity of the algorithm is O ( n 2 / k ), where n is the number of attribute values and k is the number of processors, each step is a hardware clock cycle of 25 ns. Thus, a single chip can yield a throughput rate of 2.56 giga results per second operating at a rate of 40 MHz. Higher throughputs can be obtained by cascading multiple chips in a serial fashion.