论文信息 - P/sup 2/ID in a modern CMOS technology

P/sup 2/ID in a modern CMOS technology

Plasma process induced damage has been widely investigated in the past few years. We present in this work results from a yearlong study intended to reduce plasma-induced damage in a modern CMOS technology, featuring ultra thin gate oxide. We studied both nMOSFETs and pMOSFETs with a physical gate oxide thickness of 3.5 nm.

[1] Koichi Hashimoto,et al. New Phenomena of Charge Damage in Plasma Etching: Heavy Damage Only through Dense-Line Antenna , 1993 .

[2] Horng-Chih Lin,et al. Resist-related damage on ultrathin gate oxide during plasma ashing , 1997 .

[3] Horng-Chih Lin,et al. Evaluation of plasma charging damage in ultrathin gate oxides , 1998 .

[4] Konstantinos P. Giapis,et al. Modeling of charging damage during interlevel oxide deposition in high-density plasmas , 1998 .

[5] Kin P. Cheung,et al. Plasma Charging Damage , 2000 .

[6] Alessandro Paccagnella,et al. Low-field latent plasma damage depassivation in thin-oxide MOS , 2000 .