Ultra Low Power Single-ended 6T SRAM Using 40 nm CMOS Technology*

An ultra low power SRAM cell design is proposed in this investigation. The supply voltage of the SRAM is gated by wordline (WL) enable to select the corresponding supply voltage. If the WL of the cell is not asserted, a lower voltage is selected to keep the status of the stored bit such that the entire standby power is reduced. By contrast, as soon as the WL of the cell is enabled to execute either read or write (R/W), the normal supply voltage will be activated to proceed the R/W operation. Theoretical derivation as well as all-PVT-corner simulations are provided to verify the functional correctness and performance. A 1 kb SRAM design based on the proposed cell with BIST and PDP (power-delay production) reduction circuit is demonstrated to show the energy/access is as low as 0.034 pJ, which is by far the best to date.

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