Asynchronous low power VLSI implementation of the International Data Encryption Algorithm
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[1] A.L. Sangiovanni-Vincentelli,et al. Synthesis of hazard-free asynchronous circuits with bounded wire delays , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Steven M. Nowick,et al. Asynchronous Circuit Design: Motivation, Background, & Methods , 1995 .
[3] Steven M. Nowick. Design of a low-latency asynchronous adder using speculative completion , 1996 .
[4] Xuejia Lai,et al. Markov Ciphers and Differential Cryptanalysis , 1991, EUROCRYPT.
[5] Scott Hauck,et al. Asynchronous design methodologies: an overview , 1995, Proc. IEEE.
[6] R. Brodersen,et al. A fully-asynchronous digital signal processor using self-timed circuits , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.
[7] Robert W. Brodersen,et al. A fully-asynchronous digital signal processor using self-timed circuits , 1990 .
[8] Peter A. Beerel,et al. Estimation of energy consumption in speed-independent control circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Chu Shik Jhon,et al. Direct synthesis of efficient speed-independent circuits from deterministic signal transition graphs , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.
[10] Wolfgang Fichtner,et al. A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm , 1994 .
[11] Xuejia Lai,et al. A Proposal for a New Block Encryption Standard , 1991, EUROCRYPT.