Improved performance of IBM Enterprise System/9000 bipolar logic chips

The performance required for logic gate arrays by the IBM Enterprise System/9000TM (ES/9000TM) family of water-cooled processors was obtained by redesigning chips that previously consisted of emitter-coupled logic (ECL) circuits. Multiple bipolar logic circuit families were implemented for the first time on a single IBM chip by using a modular cell approach. In 60% of the ECL circuits, ac coupling in ECL gates reduced the maximum operating power per ECL circuit on ES/9000 chips by S0% and decreased the signal delay per loaded gate by 30%, to 150 ps. About 10-20% of the remaining ECL circuits were replaced by differential current switches (DCS) which dissipated less power and improved the overall chip performance. Circuits to communicate between ECL and DCS circuit families and to improve DCS circuit reliability were included on the ES/9000 chips without affecting logic function density. Introduction Recent advances in bipolar logic semiconductor processing have increased circuit densities on a cliip by an order of magnitude [1, 2]. However, packaging improvements have only doubled the quantity of heat that can be removed from a chip [3]. Consequently, a 50% reduction in the average operating power per logic circuit is required. Bipolar chips in IBM 3090TM processors are composed of ECL circuits which operate at high (15 mW/single phase) power and dissipate significant quantities of heat. In ES/9000 chips, a decrease in power per circuit increases the delays due to the load associated with the capacitance of interconnecting wires. The interconnections introduce a measure of circuit loading which doubles the sensitivity of a circuit's performance to fan-out and wire lengths. Vertical geometry device design improvements reduce delays with intrinsic, but not extrinsic, loads. Advanced metallurgies do not compensate for the high wiring capacitance that arises from the longer wire lengths due to a doubling of the ES/9000 chip areas. The performance of gate arrays required by the ES/9000 family of mainframe