Physical CAD changes to incorporate design for lithography and manufacturability

The next few process generations (65 nm and below) will have serious lithography and manufacturing constraints since the feature size is shrinking much more rapidly than the wavelengths used in manufacturing the chips. This paper starts with a quick tutorial on the Design for Manufacturability problems of these process generations, concentrating primarily on the limitations of optical lithography. The remainder of the talk covers the changes to physical design tools, such as placement and routing, that are needed to cope with these problems.

[1]  F.M. Schellenberg,et al.  Adoption of OPC and the impact on design and layout , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[2]  Wojciech Maly,et al.  Computer-aided design for VLSI circuit manufacturability , 1990, Proc. IEEE.

[3]  Puneet Gupta,et al.  Performance-impact limited area fill synthesis , 2003, DAC '03.

[4]  Lars Liebmann,et al.  TCAD development for lithography resolution enhancement , 2001, IBM J. Res. Dev..

[5]  T. C. Huang,et al.  Numerical modeling and characterization of the stress migration behaviour upon various 90 nanometer Cu/Low k interconnects , 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

[6]  Hardy Kwok-Shing Leung,et al.  Advanced routing in changing technology landscape , 2003, ISPD '03.

[7]  Michael L. Rieger,et al.  Layout design methodolgies for sub-wavelength manufacturing , 2001, DAC '01.

[8]  Andrew B. Kahng,et al.  Area fill synthesis for uniform layout density , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Andrew B. Kahng,et al.  Subwavelength lithography and its potential impact on design and EDA , 1999, DAC '99.

[10]  Lars W. Liebmann,et al.  Resolution enhancement techniques in optical lithography: It's not just a mask problem , 2001, Photomask Japan.

[11]  H. Kaneko,et al.  Stress-induced voiding phenomena for an actual CMOS LSI interconnects , 2002, Digest. International Electron Devices Meeting,.

[12]  S. C. Lin,et al.  Stress-induced voiding and its geometry dependency characterization , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..