FPGA Implementations of Feed Forward Neural Network by using Floating Point Hardware Accelerators

This paper documents the research towards the analysis of dierent solutions to implement a Neu- ral Network architecture on a FPGA design by using floating point accelerators. In particular, two dierent implementations are investigated: a high level solution to create a neural network on a soft processor design, with dierent strategies for enhancing the performance of the process; a low level solution, achieved by a cas- cade of floating point arithmetic elements. Compar- isons of the achieved performance in terms of both time consumptions and FPGA resources employed for the architectures are presented.

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