Reading Between the Dies: Cross-SLR Covert Channels on Multi-Tenant Cloud FPGAs

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly available via commercial cloud providers, which currently allocate devices on a per-user basis. As the underlying hardware is often underutilized, several proposals for multi-tenant use of FPGA resources have been brought forth, along with some initial work on security attacks in this setting. Simultaneously, high-end FPGAs are being produced with 2.5D integration of multiple distinct dies, called Super Logic Regions (SLRs), onto the same chip. Although one might expect that physical separation of logic onto separate dies could prevent multi-tenant attacks, this paper demonstrates for the first time that cross-SLR information leaks based on sensing voltage changes within the FPGA chip are possible, without physical access to or modification of the boards. The cross-SLR covert channel is characterized analytically and experimentally on five Xilinx Virtex UltraScale+ FPGAs, both locally and on the Amazon and Huawei clouds. Several configurations of the source transmitters and the sink receivers are tested, including their locations, types, and sizes. The power-based channel is shown to have a bandwidth upwards of 4.6 Mbps and accuracy of over 97.6%. Consequently, as physical separation of tenants onto separate dies (SLRs) is an insufficient countermeasure against information leaks, hardware-level architectural improvements are necessary to make secure multi-tenant FPGAs on shared clouds a reality.

[1]  Jakub Szefer,et al.  Temporal Thermal Covert Channels in Cloud FPGAs , 2019, FPGA.

[2]  Ramarathnam Venkatesan,et al.  FPGAs for trusted cloud computing , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

[3]  Mehdi Baradaran Tahoori,et al.  FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES , 2018, IACR Trans. Cryptogr. Hardw. Embed. Syst..

[4]  Ken Eguro,et al.  Leakier Wires , 2019, ACM Trans. Reconfigurable Technol. Syst..

[5]  Dirk Koch,et al.  A Survey on FPGA Virtualization , 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

[6]  Zhenyu Wu,et al.  Whispers in the Hyper-Space: High-Bandwidth and Reliable Covert Channel Attacks Inside the Cloud , 2015, IEEE/ACM Transactions on Networking.

[7]  Daniel E. Holcomb,et al.  Characterizing Power Distribution Attacks in Multi-User FPGA Environments , 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

[8]  Jakub Szefer,et al.  Measuring Long Wire Leakage with Ring Oscillators in Cloud FPGAs , 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

[9]  Eric Schkufza,et al.  Sharing, Protection, and Compatibility for Reconfigurable Fabric with AmorphOS , 2018, OSDI.

[10]  Paul Chow,et al.  FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack , 2014, FCCM 2014.

[11]  Takeshi Sugawara,et al.  Oscillator without a combinatorial loop and its threat to FPGA in data centre , 2019, Electronics Letters.

[12]  Yu Zhang,et al.  Enabling FPGAs in the cloud , 2014, Conf. Computing Frontiers.

[13]  Vaughn Betz,et al.  Interconnect Solutions for Virtualized Field-Programmable Gate Arrays , 2018, IEEE Access.

[14]  Mehdi Baradaran Tahoori,et al.  An inside job: Remote power analysis attacks on FPGAs , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[15]  Daniel E. Holcomb,et al.  Characterization of Long Wire Data Leakage in Deep Submicron FPGAs , 2019, FPGA.

[16]  Ryan Kastner,et al.  Managing Security in FPGA-Based Embedded Systems , 2008, IEEE Design & Test of Computers.

[17]  Mehdi Baradaran Tahoori,et al.  Remote Inter-Chip Power Analysis Side-Channel Attacks at Board-Level , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[18]  Mehdi B. Tahoori,et al.  Checking for Electrical Level Security Threats in Bitstreams for Multi-tenant FPGAs , 2018, 2018 International Conference on Field-Programmable Technology (FPT).

[19]  Dina G. Mahmoud,et al.  Timing Violation Induced Faults in Multi-Tenant FPGAs , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[20]  Andreas Herkersdorf,et al.  Enabling FPGAs in Hyperscale Data Centers , 2015, 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom).

[21]  Christophe Bobda,et al.  Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip , 2017, ARC.

[22]  Cameron D. Patterson,et al.  Unraveling the Security Puzzle: A Distributed Framework to Build Trust in FPGAs , 2015, NSS.

[23]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[24]  Ramesh Karri,et al.  Multi-Tenant FPGA-based Reconfigurable Systems: Attacks and Defenses , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[25]  Steven Trimberger,et al.  Security of FPGAs in data centers , 2017, 2017 IEEE 2nd International Verification and Security Workshop (IVSW).

[26]  Jürgen Teich,et al.  Using the Power Side Channel of FPGAs for Communication , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

[27]  Mehdi Baradaran Tahoori,et al.  Voltage drop-based fault attacks on FPGAs using valid bitstreams , 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

[28]  Maciej Nikodem,et al.  Temperature-based covert channel in FPGA systems , 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).

[29]  Ken Eguro,et al.  FPGA side-channel receivers , 2011, FPGA '11.

[30]  G. Edward Suh,et al.  FPGA-Based Remote Power Side-Channel Attacks , 2018, 2018 IEEE Symposium on Security and Privacy (SP).

[31]  T. El-Ghazawi,et al.  Virtualizing and sharing reconfigurable resources in High-Performance Reconfigurable Computing systems , 2008, 2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications.

[32]  Daniel E. Holcomb,et al.  FPGA Side Channel Attacks without Physical Access , 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[33]  Ken Eguro,et al.  Leaky Wires: Information Leakage and Covert Communication Between FPGA Long Wires , 2016, AsiaCCS.

[34]  Meeta Srivastav,et al.  Sensing nanosecond-scale voltage attacks and natural transients in FPGAs , 2013, FPGA '13.