Semiconductor memory and memory system including semiconductor memory

The present invention relates to a memory system. The memory system comprises first and second semiconductor memories which have the same structure and have a plurality of memory cells aligned by each of columns and rows thereof; and a memory controller which controls the first and the second memories. The first and the second memories receive the same address from the memory controller. In response to the address commonly received, a first address of a first row adjacent to the memory cells selected in the first semiconductor memory is different from a second address of a second row adjacent to the memory cells selected in the second semiconductor memory.