Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques

High-Level Synthesis has emerged as a promising technology for improving FPGA designer productivity, but will only be successful if it is accompanied by a debug ecosystem. Recent efforts have presented in-system debug techniques which allow a designer to debug an implementation, running on an FPGA, in the context of the original source code. These techniques typically store a history of all user variables on chip. To maximize the effectiveness of the on-chip memory, it is desirable to store only selected user variables. Unfortunately, this may lead to multiple debug runs. In existing frameworks, changing the variables to be stored between runs requires a full recompile. In this paper, we propose several flows that use incremental compilation to reduce the debug turn-around time. The first flow, in which the user circuit and instrumentation are co-optimized during compilation, gives the fastest debug clock speeds but suffers in user circuit performance once the debug instrumentation is removed. In the second flow, the optimization of the user circuit is sacrosanct. It is placed and routed first without having any constraints and the debug instrumentation is added later leading to the fastest user circuit clock speeds, but performance suffers slightly during debug. Using either flow, we achieve 40% reduction in debug turn-around times, on average.