1. Int-oduction Recently. intelligent dynarnic RAMs have been proposed to ease a cumbersome refresh timing control and to enable a battery back-up operation. Among them are a self-refresh dynamic RAM. a pseudo SRAM (PSRAM)') and a virtually SRAM (VSRAM)2). The last one completely frees the users from the refresh operation. The key circuit technology in making these intelligent DRAMs is a construction of a refresh timer, which tells the time when a refresh operation is needed. Conventionally, a ring oscillator has been used for this refresh timer. However, the voltage, temperature, and process dependencies of the ring oscillation frequency are far from being optimized. Therefore, one or two orders of magnitude higher refresh frequency is to be chosen to keep a margm, resulting in a high standby current of the RAM. A self-aligned refresh scheme, namely a leak sensor, is newly proposed in this paper to fully overcome this problem. Since the leak sensor determines the refresh intervals in a self-aligned way with the memory cell charge leakage, it offers the optimized refresh frequency. Novel preset scheme cancels the circuit instabilities caused by the process fluctuations. Leakage characteristics of a capacitor is also investigated in relation to the leak sensor. The effectiveness of the leak sensor is demonstrated by a lMbit VSRAM.