Layout method of FPGA (Field Programmable Gate Array) chip clock net

The invention relates to a layout method of an FPGA (Field Programmable Gate Array) chip clock net. The method comprises the following steps: determining a low-skew net and a common clock net in a net of the FPGA chip, wherein the net of the FPGA chip comprises a data net and a clock net, and the clock net comprises the low-skew net and the common clock net; inquiring whether a unit corresponding to a destination end of the common clock net is a register unit or not; when the unit corresponding to the destination end of the common clock net is the register unit, increasing the weight of the common clock net; according to the weight, carrying out optimization processing on the net of the FPGA chip, and obtaining the length of the net, which is subjected to the optimization processing, of the FPGA chip; and according to the length of the optimization processing common clock net, carrying out layout processing on the register unit corresponding to the destination end of the common clock net.