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[1] Ferdinando Bedeschi,et al. A Multi-Level-Cell Bipolar-Selected Phase-Change Memory , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[2] M. Wuttig,et al. Phase-change materials for rewriteable data storage. , 2007, Nature materials.
[3] Jure Leskovec,et al. {SNAP Datasets}: {Stanford} Large Network Dataset Collection , 2014 .
[4] Kuanping Shang,et al. Low-loss compact multilayer silicon nitride platform for 3D photonic integrated circuits. , 2015, Optics express.
[5] A. Cabrini,et al. Voltage-Driven Multilevel Programming in Phase Change Memories , 2009, 2009 IEEE International Workshop on Memory Technology, Design, and Testing.
[6] Vijayalakshmi Srinivasan,et al. Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.
[7] Xiaowei Li,et al. Wear rate leveling: Lifetime enhancement of PRAM with endurance variation , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).
[8] Rami G. Melhem,et al. Bit mapping for balanced PCM cell programming , 2013, ISCA.
[9] Sudeep Pasricha,et al. DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency , 2017, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID).
[10] Moinuddin K. Qureshi,et al. DEUCE: Write-Efficient Encryption for Non-Volatile Memories , 2015, ASPLOS.
[11] Shiming Gao,et al. On-chip reconfigurable optical add-drop multiplexer for hybrid wavelength/mode-division-multiplexing systems. , 2017, Optics letters.
[12] Y.C. Chen,et al. Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory , 2007, 2007 IEEE International Electron Devices Meeting.
[13] Michal Lipson,et al. WDM-compatible mode-division multiplexing on a silicon chip , 2014, Nature Communications.
[14] Thomas Taubner,et al. Reversible Optical Switching of Infrared Antenna Resonances with Ultrathin Phase-Change Layers Using Femtosecond Laser Pulses , 2014 .
[15] Joonyoung Kim,et al. HBM: Memory solution for bandwidth-hungry processors , 2014, 2014 IEEE Hot Chips 26 Symposium (HCS).
[16] Jung Hee Cheon,et al. Homomorphic Encryption for Arithmetic of Approximate Numbers , 2017, ASIACRYPT.
[17] Bruce Jacob,et al. DRAMSim2: A Cycle Accurate Memory System Simulator , 2011, IEEE Computer Architecture Letters.
[18] Zhen Liu,et al. An Adaptive Ensemble Machine Learning Model for Intrusion Detection , 2019, IEEE Access.
[19] Jennifer Widom,et al. GPS: a graph processing system , 2013, SSDBM.
[20] Hei Wong,et al. A comparative study of charge pumping circuits for flash memory applications , 2012, Microelectron. Reliab..
[21] Vijayalakshmi Srinivasan,et al. Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[22] Hyokyung Bahn,et al. Characterizing Memory Write References for Efficient Management of Hybrid PCM and DRAM Memory , 2011, 2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems.
[23] Marco Fiorentino,et al. A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[24] Aart J. C. Bik,et al. Pregel: a system for large-scale graph processing , 2010, SIGMOD Conference.
[25] Hongliang Yu,et al. Increasing Endurance and Security of Phase-Change Memory with Multi-Way Wear-Leveling , 2014, IEEE Transactions on Computers.
[26] Harish Bhaskaran,et al. Integrated all-photonic non-volatile multi-level memory , 2015, Nature Photonics.
[27] K. Bergman,et al. Energy-bandwidth design exploration of silicon photonic interconnects in 65nm CMOS , 2016, 2016 IEEE Optical Interconnects Conference (OI).
[28] Jun Yang,et al. A low power and reliable charge pump design for Phase Change Memories , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).
[29] Nathan Youngblood,et al. Integrated 256 Cell Photonic Phase-Change Memory With 512-Bit Capacity , 2020, IEEE Journal of Selected Topics in Quantum Electronics.
[30] Vladimir Stojanovic,et al. Silicon photonics for compact, energy-efficient interconnects [Invited] , 2007, Journal of Optical Networking.
[31] Christian Bernard,et al. POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems , 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[32] Yvain Thonnart,et al. WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[33] Rami G. Melhem,et al. Increasing PCM main memory lifetime , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[34] Mauro Conti,et al. A Survey on Homomorphic Encryption Schemes: Theory and Implementation , 2017 .
[35] Nathan Youngblood,et al. Experimental investigation of silicon and silicon nitride platforms for phase-change photonic in-memory computing , 2020, Optica.
[36] David A. Patterson,et al. The GAP Benchmark Suite , 2015, ArXiv.
[37] Karthick Rajamani,et al. Energy Management for Commercial Servers , 2003, Computer.
[38] Sandro Bartolini,et al. Design Options for Optical Ring Interconnect in Future Client Devices , 2014, JETC.
[39] David H. Bailey,et al. The Nas Parallel Benchmarks , 1991, Int. J. High Perform. Comput. Appl..
[40] Masaya Notomi,et al. Toward fJ/bit optical communication in a chip , 2014 .
[41] D. Pappalardo,et al. Charge Pump Circuits: An Overview on Design Strategies and Topologies , 2010, IEEE Circuits and Systems Magazine.
[42] Jun Yang,et al. FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.
[43] Christopher Batten,et al. Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics , 2009, IEEE Micro.
[44] Onur Mutlu,et al. Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.
[45] Linjie Zhou,et al. All-optical non-volatile tuning of an AMZI-coupled ring resonator with GST phase-change material. , 2018, Optics letters.
[46] Shih-Hung Chen,et al. Phase-change random access memory: A scalable technology , 2008, IBM J. Res. Dev..
[47] Guangjie Han,et al. Dynamic Adaptive Replacement Policy in Shared Last-Level Cache of DRAM/PCM Hybrid Memory for Big Data Storage , 2017, IEEE Transactions on Industrial Informatics.
[48] Chun Jason Xue,et al. SLC-enabled wear leveling for MLC PCM considering process variation , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).
[49] Andrew B. Kahng,et al. Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[50] R. Ho,et al. Energy-Efficient Photonics in Future High-Connectivity Computing Systems , 2015, Journal of Lightwave Technology.
[51] Rajeev J. Ram,et al. Single-chip microprocessor that communicates directly using light , 2015, Nature.
[52] Luis A. Lastras,et al. PreSET: Improving performance of phase change memories by exploiting asymmetry in write times , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[53] C. David Wright,et al. An optoelectronic framework enabled by low-dimensional phase-change films , 2014, Nature.
[54] Chen Sun,et al. Re-architecting DRAM with Monolithically Integrated Silicon Photonics , 2009 .
[55] Hongzhong Zheng,et al. Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling , 2014 .
[56] Tao Zhang,et al. Overcoming the challenges of crossbar resistive memory architectures , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).
[57] C. David Wright,et al. In-memory computing on a photonic platform , 2018, Science Advances.
[58] Ricardo Bianchini,et al. Page placement in hybrid memory systems , 2011, ICS '11.
[59] Carlos Guestrin,et al. Distributed GraphLab : A Framework for Machine Learning and Data Mining in the Cloud , 2012 .
[60] William J. Dally,et al. Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).
[61] Ke Xu,et al. Mode-Division Multiplexing for Silicon Photonic Network-on-Chip , 2017, Journal of Lightwave Technology.
[62] Nagarajan Kandasamy,et al. Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories , 2019, ACM Trans. Embed. Comput. Syst..
[63] Jianmin Wang,et al. Overview of Phase-Change Materials Based Photonic Devices , 2020, IEEE Access.
[64] S. Ovshinsky. Reversible Electrical Switching Phenomena in Disordered Structures , 1968 .
[65] Joseph Gonzalez,et al. PowerGraph: Distributed Graph-Parallel Computation on Natural Graphs , 2012, OSDI.
[66] Ajay Joshi,et al. Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[67] Seong Keun Kim,et al. Future of dynamic random-access memory as main memory , 2018 .
[68] C. David Wright,et al. On‐Chip Photonic Memory Elements Employing Phase‐Change Materials , 2014, Advanced materials.
[69] Tao Zhang,et al. NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems , 2015, IEEE Computer Architecture Letters.
[70] K. Bergman,et al. Resolving the thermal challenges for silicon microring resonator devices , 2014 .
[71] Thomas Taubner,et al. Phase-change materials for non-volatile photonic applications , 2017, Nature Photonics.
[72] Jongman Kim,et al. An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).
[73] C. David Wright,et al. Fast and reliable storage using a 5 bit, nonvolatile photonic memory cell , 2018, Optica.
[74] Weisong Shi,et al. Edge Computing: Vision and Challenges , 2016, IEEE Internet of Things Journal.
[75] Mark Chen,et al. Language Models are Few-Shot Learners , 2020, NeurIPS.
[76] A. Biberman,et al. Ultrahigh-Bandwidth Silicon Photonic Nanowire Waveguides for On-Chip Networks , 2008, IEEE Photonics Technology Letters.
[77] Jian Huang,et al. LL-PCM: Low-Latency Phase Change Memory Architecture , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).
[78] K. Gopalakrishnan,et al. Phase change memory technology , 2010, 1001.1164.
[79] Hsien-Hsin S. Lee,et al. Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping , 2010, ISCA.
[80] Qi Wang,et al. A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth , 2012, 2012 IEEE International Solid-State Circuits Conference.
[81] Onur Mutlu,et al. Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories , 2014, ACM Trans. Archit. Code Optim..
[82] Four Channel 48Gbps Multicasting in a Coupled Si Ring Resonator with Tunable Channel Spacing , 2018, 2018 Conference on Lasers and Electro-Optics Pacific Rim (CLEO-PR).
[83] Yong-Zhen Huang,et al. Silicon nitride three-mode division multiplexing and wavelength-division multiplexing using asymmetrical directional couplers and microring resonators. , 2014, Optics express.
[84] Yvain Thonnart,et al. PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs , 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[85] Andrew Alduino,et al. Demonstration of a high speed 4-channel integrated silicon photonics WDM link with hybrid silicon lasers , 2010, 2010 IEEE Hot Chips 22 Symposium (HCS).
[86] Onur Mutlu,et al. Memory scaling: A systems architecture perspective , 2013, 2013 5th IEEE International Memory Workshop.
[87] Nikolaos Hardavellas,et al. Galaxy: a high-performance energy-efficient multi-chip architecture using photonic interconnects , 2014, ICS '14.
[88] Mohammad Arjomand,et al. Boosting Access Parallelism to PCM-Based Main Memory , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).
[89] C. Wright,et al. Behavioral modeling of integrated phase-change photonic devices for neuromorphic computing applications , 2019, APL Materials.
[90] Christopher Batten,et al. Designing Chip-Level Nanophotonic Interconnection Networks , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
[91] Jin Xiong,et al. DWC: dynamic write consolidation for phase change memory systems , 2014, ICS '14.
[92] Cong Xu,et al. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[93] Jun Yang,et al. Improving write operations in MLC phase change memory , 2012, IEEE International Symposium on High-Performance Comp Architecture.
[94] Sang Woon Lee,et al. Capacitors with an Equivalent Oxide Thickness of <0.5 nm for Nanoscale Electronic Semiconductor Memory , 2010 .
[95] J Feldmann,et al. Calculating with light using a chip-scale all-optical abacus , 2017, Nature Communications.
[96] Mark Wade,et al. TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O , 2020, IEEE Micro.