Visual simulator for ILP dynamic OOO processor
暂无分享,去创建一个
[1] Péter Kacsuk,et al. Advanced Computer Architectures , 1997 .
[2] David W. Wall,et al. Limits of instruction-level parallelism , 1991, ASPLOS IV.
[3] Donald J. Patterson,et al. Computer organization and design: the hardware-software interface (appendix a , 1993 .
[4] David A. Patterson,et al. Computer architecture (2nd ed.): a quantitative approach , 1996 .
[5] David A. Patterson,et al. Computer organization and design (2nd ed.): the hardware/software interface , 1997 .
[6] Andrew R. Pleszkun,et al. Implementing Precise Interrupts in Pipelined Processors , 1988, IEEE Trans. Computers.
[7] Norman P. Jouppi,et al. Register file design considerations in dynamically scheduled processors , 1996, Proceedings. Second International Symposium on High-Performance Computer Architecture.
[8] J. Gonz. Idetifying Contributing Factors to ILP , 1996 .
[9] David W. Wall,et al. Speculative Execution and Instruction-Level Parallelism , 1999 .
[10] Todd M. Austin,et al. The SimpleScalar tool set, version 2.0 , 1997, CARN.
[11] Gary S. Tyson,et al. Improving the accuracy and performance of memory communication through renaming , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.
[12] Péter Kacsuk,et al. Advanced computer architectures - a design space approach , 1997, International computer science series.
[13] J. Stanley Warford. Computer Systems , 1998 .
[14] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[15] Todd M. Austin,et al. Dynamic dependency analysis of ordinary programs , 1992, ISCA '92.