Extending OPMISR beyond 10x Scan Test Efficiency

Rapidly increasing ASIC gate counts are stressing the test capacity of manufacturing test equipment. New on-product multiple-input signature register (OPMISR) techniques compress test vectors produced by ATPG, substantially reducing data volume and test time.

[1]  Janak H. Patel,et al.  A case study on the implementation of the Illinois Scan Architecture , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[2]  Brion L. Keller,et al.  OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[3]  Janak H. Patel,et al.  Reducing test application time for full scan embedded cores , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).

[4]  Helmut Lang,et al.  Using on-chip test pattern compression for full scan SoC designs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[5]  Nur A. Touba,et al.  Reducing test data volume using external/LBIST hybrid test patterns , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[6]  Alex Orailoglu,et al.  Test volume and application time reduction through scan chain concealment , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[7]  Krishnendu Chakrabarty,et al.  Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[8]  Janusz Rajski,et al.  Logic BIST for large industrial designs: real issues and case studies , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[9]  Kuen-Jong Lee,et al.  Using a single input to support multiple scan chains , 1998, ICCAD '98.

[10]  Brion L. Keller,et al.  A SmartBIST variant with guaranteed encoding , 2001, Proceedings 10th Asian Test Symposium.